2.2.1. Clocking and reset

All ports are asynchronous and active high except the ones where stated opposite. Inputs and outputs are not registered (except where it is indicated) to reach zero latency SRAM accesses and transaction bypass where it is possible.

Table 2.1. Clock and reset signals

Signal NameDirectionDescription
HCLKInputAHB Bus clock. This clock is used for all always on logic.
PCLKGInputGated clock input for register interface (APB). It must be the same frequency and same phase as HCLK. Can be gated, when there are no APB activities. It is expected to run while APB interface PSEL signal is asserted.
HRESETnInputActive low asynchronous AHB reset. Reset all or a subset of the CG092 registers depending on the RESET_ALL_REGS parameter.

HCLK and PCLKG clocks are handled as synchronous clocks by the design internally.

HCLK must not be gated even if the CG092 is disabled because the AHB data path multiplexing logics requires it for proper operation.

Copyright © 2016. All rights reserved.ARM DDI 0569A