2.3.4. Enabling the cache

The tables in this section use the following terminology:

APOW

Automatic Power Control: CCR.SET_MAN_POW= 0 selects automatic cache RAM power control mode.

AINV

Automatic Invalidation request: CCR.SET_MAN_INV = 0 selects automatic cache invalidate.

SRAM resource

SRAM resource are considered to be an CG092 resource.

SRAM resource request

CG092 requests access to SRAMs (using RAMPWRUPREQ).

SRAM resource availability

SRAMs are accessible for read and write (indicated by RAMPWRUPACK).

The following table describes how to enable the CG092 with different configuration settings if the SRAM content is invalid, such as at power on.

Table 2.9. Cache enable with invalid SRAM contents

APOW AINVControl sequence
00
  1. Check that cache is disabled (SR[1:0]=0).

  2. Manual power request.

  3. Wait until SRAM resource is available and SR[4] is set.

  4. Issue manual invalidate request.

  5. Wait until invalidate request has completed and CCR[1]=0.

  6. Enable cache.

01
  1. Check that cache is disabled (SR[1:0]=0).

  2. Manual power request.

  3. Wait until SRAM resource is available and SR[4] is set.

  4. Enable cache.

Note

Enabling cache before SRAMs are accessible causes a power error.

10

Caution

Not supported.

Not deterministic behavior.

11
  1. Check that cache is disabled (SR[1:0]=0).

  2. Enable cache.


The following table describes how to enable the CG092 with different configuration settings if the SRAM contents are valid, such as a wake up from retention.

Table 2.10. Cache enable with invalid SRAM contents

APOW AINVControl sequence
00
  1. Check that cache is disabled (SR[1:0]=0).

  2. Issue manual power request.

  3. Wait until SRAM resource is available and SR[4] is set.

  4. Enable cache.

Note

Enabling cache before SRAMs are accessible causes a power error.

01

Caution

Not supported.

Not deterministic behavior.

10
  1. Check that cache is disabled (SR[1:0]=0).

  2. Enable cache.

11

Caution

Not supported.

Not deterministic behavior.


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