2.2.4. Statistics ports

Statistics ports are present and always driven. The following table lists the interface signals.

Table 2.4. Statistics interface

Signal NameDirectionDescription
CACHEMISSOutput

Active high single cycle pulses indicating that a cache miss happened during cache look up.

Port is registered and synchronous to HCLK.

CACHEHITOutput

Active high single cycle pulses indicating that a cache hit happened during cache look up.

Port is registered and synchronous to HCLK.


The system designer can select generation of status registers that count cache hits and misses.

If more detailed statistics are required, the SoC designer can use the CACHEHIT and CACHEMISS signals and implement custom statistics collection logic. See Cache Statistic Hit Register, CSHR and Cache Statistic Miss Register, CSMR.

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