2.2.3. Interrupt request

The CG092 implements one interrupt output port (IRQ) and handles the following interrupts:

In addition to the HW interrupt signal, you can determine the interrupt state by reading the IRQSTAT interrupt status register.

The following table describes the interrupt interface:

Table 2.3. Interrupt request interface signals

Signal NameDirectionDescription
IRQOutput

Interrupt request line. Interrupt request is an active high level signal.

Port is registered and synchronous to HCLK.


Power error interrupt

This interrupt occurs if the CG092 is enabled while the SRAM resource is removed.

This error type indicates that either:

  • The external SRAM resource is not available (RAMPWRUPACK = 0b0 and SR.POW_STAT = 0b0)

  • The CG092 is instructed to deassert RAMPWRUPREQ while the cache is enabled thus it would cause an error to power down the SRAMs.

The power error interrupt is raised if any of the following conditions are met:

  • The CG092 is enabled when SRAM resource is removed.

  • The CG092 is instructed to make a manual invalidation while SRAM resource was not available or removed.

  • The CG092 is enabled and operates in manual power request mode while it is instructed to release SRAM resource (CCR.POW_REQ=0). In this case the power request is not cleared, but the cache disables itself due to the error interrupt.

Manual invalidation error interrupt

This interrupt occurs if the manual invalidate process starts and the CG092 is enabled.

Manual invalidation process must not be running while the CG092 is enabled, because an incoming cacheable read transaction can corrupt the invalidation process and the cache might return an invalid read response. Manual invalidation error occurs when manual invalidation request has happened when the CG092 was enabled.

On error detection:

  1. The cache prevents the start of the invalidation process

  2. Clears the CCR.INV_REQ bit.

  3. Raises an interrupt request if it is not masked and disables the cache.

To resume normal operation:

  1. Clear the interrupt request

  2. Re-initiate a manual or automatic invalidation.

Interrupt masking

Interrupts can be masked from the IRQMASK register. The cause of the interrupt request indication can be read from the IRQSTAT interrupt status register. The user can clear an interrupt by writing 0b1 to the corresponding status bitfield.

Each type of error interrupt regardless of the IRQMASK setting disables the cache to safely bypass all transaction and clears the CCR.EN bit.

The CG092 cannot be enabled again (CCR.EN bit set) until the error cause is resolved and the corresponding IRQSTAT bitfield is cleared.

To resume normal operation, the cache must be re-initiated with invalidation according to the programming sequences described in the Functional Description section.

Note

Invalidation is required because the CG092 cannot indicate whether an SRAM write caused the interrupt, thus SRAM content might be corrupted.

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