2.2.9. Cache Line Data SRAM

The following requirements are made on the external system:

Table 2.7. Cache SRAM interface for way 0 Cache Line Data (CLD) SRAM

Signal NameDirectionDescription
RAMCLD0ADDR[CW-5:0]OutputParametrized width data address bus
RAMCLD0WEOutputWrite control (same cycle as address)
RAMCLD0RD[3:0]OutputRead control (same cycle as address)
RAMCLD0CS[3:0]OutputChip select (same cycle as address)
RAMCLD0WDATA[127:0]OutputWrite data (same cycle as address)
RAMCLD0RDATA[127:0]InputRead data (1 cycle after address)

Table 2.8. Cache SRAM interface for way 1 Cache Line Data (CLD) SRAM

Signal NameDirectionDescription
RAMCLD1ADDR[CW-5:0]OutputParametrized width data address bus
RAMCLD1WEOutputWrite control (same cycle as address)
RAMCLD1RD[3:0]OutputRead control (same cycle as address)
RAMCLD1CS[3:0]OutputChip select (same cycle as address)
RAMCLD1WDATA[127:0]OutputWrite data (same cycle as address)
RAMCLD1RDATA[127:0]InputRead data (1 cycle after address) Tie this port either low or high if direct mapped cache type is set (CACHE_WAY = 1).

Note

CLD SRAM interface read (RD) and chip select (CS) ports are 4-bit vectors while the write enable (WE) is only a single bit port. The CG092 always updates a full 128bit line, while during a cache hit only 32-bit portion of a full 128-bit line is read to save some power.

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