HBURST is tied to 0b000. The CG092 component always makes SINGLE transfers.

HMASTLOCK is tied to 0b0. Locked transfers are not supported.

HTRANSM[0] is tied to LOW inside the cache thus it will not propagates transfers from AHB slave to AHB master interface unmodified even in bypass mode. SEQ transfers are translated to NONSEQ transfers while BUSY transfers are translated to IDLE transfers.

From the time the CG092 is enabled, the direct connection between the AHB Slave and Master interface is closed.

The CG092 drives HTRANSM to IDLE and makes only NSEQ transaction if a bypass, linefill or prefetch transaction must to be executed.

HSELM is continuously driven with 0b1 and transactions received with HSELS 0b0 on the AHB slave interface are not propagated to the AHB master interface. (HTRANSM remains in IDLE)

The CG092 is transparent if disabled, therefore if a master/interconnect driving the AHB slave interface cancels/terminates a burst, this will appear on the AHB master interface The control signals might change on the AHB master interface during a waited transfer (terminating and starting a new address phase)