2.2.8. Cache TAG SRAM

TAG SRAM clocks must have the same frequency as HCLK.

The CG092 expects the read data on the next rising clock edge after the read request was asserted (single cycle access).


The TAG SRAM data bus width depends on the configuration options made by the implementation engineer.

Table 2.5. Cache interface for way 0 TAG SRAM

Signal NameDirectionDescription
RAMTAG0ADDR[CW-5:0]OutputParameterized width data address bus
RAMTAG0WEOutputWrite control (same cycle as address)
RAMTAG0RDOutputRead control (same cycle as address)
RAMTAG0CSOutputChip select (same cycle as address)
RAMTAG0WDATA[(AW-CW):0]OutputWrite data (same cycle as address)
RAMTAG0RDATA[(AW-CW):0]InputRead data (1 cycle after address)

Table 2.6. Cache interface for way 1 TAG SRAM

Signal NameDirectionDescription
RAMTAG1ADDR[CW-5:0]OutputParametrized width data address bus
RAMTAG1WEOutputWrite control (same cycle as address)
RAMTAG1RDOutputRead control (same cycle as address)
RAMTAG1CSOutputChip select (same cycle as address)
RAMTAG1WDATA[(AW-CW):0]OutputWrite data (same cycle as address)
RAMTAG1RDATA[(AW-CW):0]InputRead data (1 cycle after address). Tie this port either low or high if direct mapped cache type is set (CACHE_WAY = 1).

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