2.3.2. Cache enabled

The following operating modes are possible if the cache is enabled:

Bypass

When the CG092 is enabled and fully operational it works as an instruction cache thus all write, debug and non-cacheable accesses are bypassed. One cycle latency is required per transfer, and the latency can increase if there is an on-going pre-fetch access in the downstream AHB.

Cache hit

If a cacheable read transaction data is found in the cache memory (cache hit) no transaction will be generated on the AHB master interface. Cache sends OKAY response on the AHB slave interface with the looked up data. No wait state is required.

Linefill

Cache miss happens when cacheable read transaction data is looked up but not found in the cache memory. Cache miss events cause linefill transactions on the AHB master port with the following properties:

  • Transfer type NONSEQ (HTRANSM[1:0] = 0b10)

  • Transfer size 4-word line (HSIZEM[2:0] = 0b100)

  • Fixed cacheable and bufferable protection control (HPROTM[3] = 1 and HRPOTM[2] = 1)

  • All other properties are set according the incoming read transaction causing the linefill

The CG092 stores the linefill data in the cache memory and sends a response on the AHB slave interface as well. One cycle latency is required per transfer, and the latency can increase if there is an on-going pre-fetch access in the downstream AHB.

Prefetch

The pre-fetch feature is a programmable option. When the prefetch feature is enabled by CCR.SET_PREFETCH, the design does the prefetch after linefill if the following conditions are true:

  • The transaction causing linefill is opcode fetch (HPROTS[0] = 0)

  • The data in the linefill buffer has already been written to SRAM

  • The downstream AHB bus is free

Prefetch transactions on the AHB master port are generated with the following properties:

  • Transfer type NONSEQ (HTRANSM[1:0] = 0b10)

  • Transfer size 4-word line (HSIZEM[2:0] = 0b100)

  • Fix cacheable, bufferable and opcode fetch protection control (HPROTM[3] = 1, HRPOTM[2] = 1 and HPROTM[0] = 0)

  • All other properties are set according the previous linefill transaction. (Address is incremented with 0x10).

Note

The prefetching performance impact is application dependent and might have a negative impact on eFlash power consumption.

The prefetch feature only helps if the code has not been cached. In many cases, the performance of the system might be reduced by prefetching because, once the prefetch is started, it cannot be abandoned. For example, if two cache misses occur, the flash must finish the prefetch access before reading the data requested by the processor.

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