2.3.7. Performance monitoring logic

Both cache hit and cache miss pulses can be counted separately by 32-bit internal registers that saturate at 0xFFFF_FFFF. The hit/miss counters value can be read from the CSHR and CSMR registers and can be cleared by a write access to the desired register.

Note

Cache hit/miss counters are optional. The SoC designer must set configuration parameter GEN_STAT_LOGIC to 1 to generate the related counter logic.

The CACHEHIT and CACHEMISS signals are always enabled however, and can be used by external performance monitoring logic.

Cache hit

The cache hit event is an active-high single cycle pulse generated when an incoming cacheable read transaction (no debug access counted) requested data is found in the cache memory (buffers, SRAMs). Cache hit event pulses are ported to CACHEHIT output.

Cache miss

The cache miss event is an active high single cycle pulse generated when an incoming cacheable read transaction (no debug access counted) requested data is not found in the cache memory (buffers, SRAMs). Cache miss event pulses are ported to CACHEMISS output.

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