3.4.1. Auto power and auto invalidate mode

This section describes enable and disable sequences when in the auto power and auto invalidate mode.

Enabling the cache

To enable the cache:

  1. Set the operation mode by setting the CCR.SET_MAN_POW bit to 0 and the CCR.SET_MAN_INV bit to 0.

    (Set register CCR to 0x00, which is the reset value.)

  2. Enable Cache by setting the CCR.EN bit to 1.

    (Set register CCR to 0x01,)

  3. Optionally wait until the SR.CS bits are equal to 2 which indicates that the cache is enabled.

Disabling the cache

To disable the cache:

  1. Set the CCR.EN bit to 0.

    (Set register CCR to 0x00.)

Copyright © 2016. All rights reserved.ARM DDI 0569A
Non-ConfidentialID040616