3.4.2. Manual power and auto invalidate mode

This section describes enable and disable sequences when in the manual power and auto invalidate mode.

Enabling the cache

To enable the cache:

  1. Set operation mode by setting the CCR.SET_MAN_POW bit to 1 and the CCR.SET_MAN_INV bit to 0.

    (Set register CCR to 0x08.)

  2. Request power by setting the CCR.POW_REQ bit to 1.

    (Set CCR to 0x0C.)

  3. Wait until the SR.POW_STAT bits are equal to 1 which indicates that the power up has completed.

  4. Enable the cache by setting the CCR.EN bit to 1.

    (Set register CCR to 0x0D.)

Disabling the cache

To disable the cache:

  1. Set the CCR.EN bit to 0.

    (Set register CCR to 0xC,)

  2. Optionally power down the SRAMs by setting the CCR.POW_REQ bit to 0.

    (Set register CCR to 0x18.)

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