3.4.3. Manual power and manual invalidate mode

This section describes enable and disable sequences when in the manual power and manual invalidate mode.

Enabling the cache and invalidating the SRAM

To enable the cache:

  1. Set operation mode by setting the CCR.SET_MAN_POW bit to 1 and bit CCR.SET_MAN_INV to 1.

    (Set register CCR to 0x18.)

  2. Request power by setting the CCR.POW_REQ bit to1.

    (Set register CCR to 0x1C.)

  3. Wait until the SR.POW_STAT bits are equal to 1 which indicates that power up has completed.

  4. Request manual invalidation by setting the CCR.INV_REQ bit to 1.

    (Set register CCR to 0x1E.)

  5. Wait until the CCR.INV_REQ bits are equal to 0 which indicates that the invalidation has finished.

  6. Enable the cache by setting the CCR.EN bit to 1.

    (Set register CCR to 0x1D.)

Enabling the cache without invalidating the SRAM

To enable the cache:

  1. Set operation mode by setting the CCR.SET_MAN_POW bit to 1 and the CCR.SET_MAN_INV bit to 1.

    (Set register CCR to 0x18.)

  2. Request power by setting the CCR.POW_REQ bit to1.

    (Set register CCR to 0x1C.)

  3. Wait until the SR.POW_STAT bits are equal to 1 which indicates that power up has completed.

  4. Enable the cache by setting the CCR.EN bit to 1.

    (Set register CCR to 0x1D.)

Disabling the cache

To disable the cache:

  1. Disable the cache by setting the CCR.EN bit to 0.

    (Set register CCR to 0x1C.)

  2. Optionally power down the SRAMs by setting the CCR.POW_REQ bit to 0.

    (Set register CCR to 0x18.)

Invalidating the cache

To invalidate the cache if it is enabled:

  1. Disable the cache by setting the CCR.EN bit to 0.

    (Set register CCR to 0x1C.)

  2. Wait until the SR.CS bit is equal to 0 which indicates that the cache is disabled.

  3. Request manual invalidation by setting bit CCR.INV_REQ to 1.

    (Set register CCR to 0x1E.)

  4. Wait until the CCR.INV_REQ bit is equal to 0 which indicates that the invalidation has finished.

  5. Enable the cache by setting the CCR.EN bit to 1.

    (Set register CCR to 0x1D.)

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