ARM® CoreLink™ SIE-200 System IP for Embedded Technical Reference Manual

Revision: r2p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographical Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreLink SIE-200 System IP for Embedded
1.1.1. Bus architecture
1.1.2. Design and verification components
1.2. Product revisions
2. Functional Description
2.1. AHB5 bus matrix
2.1.1. Functional description
2.1.2. Port list
2.1.3. AHB5 bus properties
2.2. AHB5 default slave
2.2.1. Functional description
2.2.2. Port list
2.2.3. AHB5 bus properties
2.3. AHB5 example slave
2.3.1. Functional description
2.3.2. Port list
2.3.3. AHB5 bus properties
2.4. AHB5 exclusive access monitor
2.4.1. Functional description
2.4.2. Port list
2.4.3. AHB5 bus properties
2.5. AHB5 GPIO
2.5.1. Functional description
2.5.2. Port list
2.5.3. AHB5 bus properties
2.6. AHB5 master multiplexer
2.6.1. Functional description
2.6.2. Port list
2.6.3. AHB5 bus properties
2.7. AHB5 slave multiplexer
2.7.1. Functional description
2.7.2. Port list
2.7.3. AHB5 bus properties
2.8. AHB5 timeout monitor
2.8.1. Functional description
2.8.2. Port list
2.8.3. AHB5 bus properties
2.9. AHB5 to external SRAM interface
2.9.1. Functional description
2.9.2. Port list
2.9.3. AHB5 bus properties
2.9.4. Read and write timing
2.10. AHB5 to ROM interface
2.10.1. Functional description
2.10.2. Port list
2.10.3. AHB5 bus properties
2.10.4. Read timing
2.11. AHB5 to internal SRAM interface module
2.11.1. Functional description
2.11.2. Port list
2.11.3. AHB5 bus properties
2.11.4. Read and write timing
2.12. Cortex-M3/Cortex-M4 AHB5 adapter
2.12.1. Functional description
2.12.2. Port list
2.12.3. AHB5 bus properties
2.13. AHB5 access control gate
2.13.1. Functional description
2.13.2. Port list
2.13.3. AHB5 bus properties
2.14. AHB5 downsizer
2.14.1. Functional description
2.14.2. Port list
2.14.3. AHB5 bus properties
2.15. AHB5 to AHB5 and APB4 asynchronous bridge
2.15.1. Functional description
2.15.2. Port list
2.15.3. AHB5 bus properties
2.15.4. Read and write latencies
2.16. AHB5 to AHB5 sync-down bridge
2.16.1. Functional description
2.16.2. Port list
2.16.3. AHB5 bus properties
2.16.4. Read and write latencies
2.17. AHB5 to AHB5 synchronous bridge
2.17.1. Functional description
2.17.2. Port list
2.17.3. AHB5 bus properties
2.17.4. Read and write latencies
2.18. AHB5 to AHB5 sync-up bridge
2.18.1. Functional description
2.18.2. Port list
2.18.3. AHB5 bus properties
2.18.4. Read and write latencies
2.19. AHB5 to APB4 asynchronous bridge
2.19.1. Functional description
2.19.2. Port list
2.19.3. AHB5 bus properties
2.19.4. Read and write latencies
2.20. AHB5 to APB4 sync-down bridge
2.20.1. Functional description
2.20.2. Port list
2.20.3. AHB5 bus properties
2.20.4. Read and write latencies
2.21. AHB5 upsizer
2.21.1. Functional description
2.21.2. Port list
2.21.3. AHB5 bus properties
2.22. AHB5 TrustZone master security controller
2.22.1. Functional description
2.22.2. Port list
2.22.3. AHB5 bus properties
2.23. AHB5 TrustZone memory protection controller
2.23.1. Functional description
2.23.2. Port list
2.23.3. AHB5 bus properties
2.24. AHB5 TrustZone peripheral protection controller
2.24.1. Functional description
2.24.2. Port list
2.24.3. AHB5 bus properties
2.25. APB4 TrustZone peripheral protection controller
2.25.1. Functional description
2.25.2. Port list
2.25.3. APB4 bus properties
2.26. AHB5 FRBM
2.26.1. Functional description
2.26.2. Port list
2.26.3. AHB5 bus properties
2.27. Behavioral SRAM model with an AHB5 interface
2.27.1. Functional description
2.27.2. Port list
2.28. External asynchronous 8-bit SRAM model
2.28.1. Functional description
2.28.2. Port list
2.29. External asynchronous 16-bit SRAM model
2.29.1. Functional description
2.29.2. Port list
2.30. FPGA SRAM synthesizable model
2.30.1. Functional description
2.30.2. Port list
2.31. RAM wrapper model
2.31.1. Functional description
2.31.2. Port list
2.31.3. AHB5 bus properties
2.32. ROM behavioral model
2.32.1. Functional description
2.32.2. Port list
2.33. ROM wrapper model
2.33.1. Functional description
2.33.2. Port list
2.33.3. AHB5 bus properties
3. Programmers Model
3.1. AHB5 example slave
3.2. ABH5 GPIO
3.3. AHB5 TrustZone memory protection controller
3.3.1. Look Up Table (LUT) examples
3.3.2. Configuration lockdown
A. Revisions

List of Figures

1. Key to timing diagram conventions
2.1. AHB 5 bus matrix
2.2. AHB5 default slave
2.3. AHB5 example slave
2.4. AHB5 exclusive access monitor
2.5. AHB5 GPIO control circuit and external interface
2.6. AHB5 master multiplexer
2.7. AHB5 slave multiplexer
2.8. AHB5 timeout monitor
2.9. AHB5 to external SRAM interface module
2.10. AHB5 to external SRAM interface read and write access timing
2.11. AHB5 to external SRAM interface read and write access timing
2.12. AHB5 to ROM interface module for 16 or 32-bit flash ROM
2.13. AHB5 to ROM read access timing with WS = 0
2.14. AHB5 to ROM read access timing with WS = 1
2.15. AHB5 to internal SRAM interface module
2.16. AHB5 to internal SRAM read access timings
2.17. AHB5 to internal SRAM write access timings
2.18. Cortex-M3/Cortex-M4 AHB5 adapter
2.19. AHB5 access control gate
2.20. AHB5 downsizer
2.21. AHB5 to AHB5 and APB4 asynchronous bridge
2.22. AHB5 to AHB5 sync-down bridge
2.23. AHB5 to AHB5 sync-down bridge read and write latencies
2.24. AHB5 to AHB5 synchronous bridge
2.25. AHB5 to AHB5 sync-up bridge
2.26. AHB5 to AHB5 sync-up bridge read and write latencies
2.27. AHB5 to APB4 asynchronous bridge
2.28. AHB5 to APB4 sync-down bridge
2.29. AHB5 to APB4 sync-down bridge read latency (hclk = pclk)
2.30. AHB5 to APB4 sycn-down bridge write latency (hclk = pclk)
2.31. AHB5 upsizer
2.32. AHB5 TrustZone master security controller
2.33. Single transfer error response
2.34. Burst transfer error response
2.35. Single transfer R(A)ZWI response
2.36. Burst transfer R(A)ZWI response
2.37. AHB5 TrustZone memory protection controller
2.38. AHB5 TrustZone peripheral protection controller
2.39. APB4 TrustZone peripheral protection controller
2.40. AHB5 FRBM
2.41. ROM wrapper model
2.42. FPGA SRAM synthesizable model
2.43. FPGA SRAM synthesizable model
2.44. FPGA SRAM synthesizable model
2.45. ROM wrapper model
2.46. ROM behavioral model
2.47. ROM wrapper model

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Revision History
Revision A4 March 2016First release for r0p0
Revision B24 June 2016Beta release for r0p0
Revision C29 July 2016Beta update for r0p0
Revision D28 September 2016First release for r1p0 LAC
Revision E16 December 2016First release for r2p0 EAC
Copyright © 2016 ARM Limited or its affiliates. All rights reserved.ARM DDI 0571E
Non-ConfidentialID010417