4.3.1. The system control register

The System Control Register (SCTLR) is a register that controls standard memory, system facilities and provides status information for functions that are implemented in the core.

Figure 4.5. SCTLR bit assignments

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Not all bits are available above EL1. The individual bits represent the following:

UCI

When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC, DC CVAC, and IC IVAU instructions. See Cache maintenance.

EE

Exception endianness. See Endianness.

0

Little endian.

1

Big endian.

EOE

Endianness of explicit data accesses at EL0. The possible values of this bit are:

0

Explicit data accesses at EL0 are little-endian.

1

Explicit data accesses at EL0 are big-endian.

WXN

Write permission implies XN (eXecute Never). See Access permissions.

0

Regions with write permission are not forced to XN.

1

Regions with write permission are forced to XN.

nTWE

Not trap WFE. A value of 1 means that WFE instructions are executed as normal.

nTWI

Not trap WFI. A value of 1 means that WFI instructions are executed as normal.

UCT

When set, enables EL0 access in AArch64 to the CTR_EL0 register.

DZE

Access to DC ZVA instruction at EL0. See Cache maintenance.

0

Execution prohibited.

1

Execution allowed.

I

Instruction cache enable. This is an enable bit for instruction caches at EL0 and EL1. Instruction accesses to cacheable Normal memory are cached.

UMA

User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64.

SED

SETEND Disable. Disables SETEND instructions at EL0 using AArch32.

0

SETEND instructions are enabled.

1

The SETEND instruction is disabled.

ITD

IT Disable. The possible values of this bit are:

0

The IT instruction is available.

1

The IT instruction is treated as a 16-bit instruction. Only another 16-bit instruction, or the first half of a 32-bit instruction, can follow. This depends upon the implementation.

CP15BEN

CP15 barrier enable. If implemented, it is an enable bit for the AArch32 CP15 DMB, DSB, and ISB barrier operations.

SA0

Stack Alignment Check Enable for EL0.

SA

Stack Alignment Check Enable.

C

Data cache enable. This is an enable bit for data caches at EL0 and EL1. Data accesses to cacheable Normal memory are cached.

A

Alignment check enable bit.

M

Enable the MMU.

Accessing the SCTLR

To access the SCTLR_ELn, use:

  MRS <Xt>, SCTLR_ELn  // Read SCTLR_ELn into Xt
  MSR SCTLR_ELn, <Xt>  // Write Xt to SCTLR_ELn

For example:

Example 4.1. Setting bits in the SCTLR

  MRS X0, SCTLR_EL1           // Read System Control Register configuration data
  ORR X0, X0, #(1 << 2)       // Set [C] bit and enable data caching
  ORR X0, X0, #(1 << 12)      // Set [I] bit and enable instruction caching
  MSR SCTLR_EL1, X0           // Write System Control Register configuration data

Note

The caches in the processor must be invalidated before caching of data and instructions is enabled in any of the Exception levels.

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