4.3. System registers

In AArch64, system configuration is controlled through system registers, and accessed using MSR and MRS instructions. This contrasts with ARMv7-A, where such registers were typically accessed through coprocessor 15 (CP15) operations. The name of a register tells you the lowest Exception level that it can be accessed from.

For example:

Registers that have the suffix _ELn have a separate, banked copy in some or all of the levels, though usually not EL0. Few system registers are accessible from EL0, although the Cache Type Register (CTR_EL0) is an example of one that can be accessible.

Code to access system registers takes the following form:

  MRS  x0, TTBR0_EL1          // Move TTBR0_EL1 into x0
  MSR  TTBR0_EL1, x0          // Move x0 into TTBR0_EL1

Previous versions of the ARM architecture have used coprocessors for system configuration. However, AArch64 does not include support for coprocessors. Table 4.5 lists only the system registers mentioned in this book.

For a complete list, see Appendix J of the ARM Architecture Reference Manual - ARMv8, for ARMv8-A architecture profile.

The table shows the Exception levels that have separate copies of each register. For example, separate Auxiliary Control Registers (ACTLRs) exist as ACTLR_EL1, ACTLR_EL2 and ACTLR_EL3.

Table 4.5. System registers

NameRegisterDescriptionAllowed values of n
ACTLR_ELnAuxiliary Control RegisterControls processor-specific features.1, 2, 3
CCSIDR_ELnCurrent Cache Size ID RegisterProvides information about the architecture of the currently selected cache. See Cache discovery.1
CLIDR_ELnCache Level ID Register

The type of cache, or caches, implemented at each level.

The Level of Coherency and Level of Unification for the cache hierarchy.

See Cache maintenance.

1, 2, 3
CNTFRQ_ELnCounter-timer Frequency RegisterReports the frequency of the system timer. See Timers.0
CNTPCT_ELnCounter-timer Physical Count RegisterHolds the 64-bit current count value. See Timers.0
CNTKCTL_ELnCounter-timer Kernel Control RegisterControls the generation of an event stream from the virtual counter. Also controls access from EL0 to the physical counter, virtual counter, EL1 physical timers, and the virtual timer. See Timers.1
CNTP_CVAL_ELnCounter-timer Physical Timer Compare Value RegisterHolds the compare value for the EL1 physical timer. See Timers.0
CPACR_ELnCoprocessor Access Control RegisterControls access to Trace, floating-point, and NEON functionality. See ISB in more detail.1
CSSELR_ELnCache Size Selection RegisterSelects the current Cache Size ID Register, CCSIDR_EL1, by specifying the required cache level and the cache type, either instruction or data cache. See Cache discovery.1
CNTP_CTL_ELnCounter-timer Physical Control RegisterControl register for the EL1 physical timer. See Timers.0
CTR_ELnCache Type RegisterInformation about the architecture of the integrated caches. See Cache discovery.0
DCZID_ELnData Cache Zero ID RegisterIndicates the block size written with byte values of 0 by the Data Cache Zero by Virtual Address (DCZVA) system instruction. See Cache discovery.0
ELR_ELnException Link RegisterHolds the address of the instruction which caused the exception. 1, 2, 3
ESR_ELnException Syndrome RegisterIncludes information about the reasons for the exception. See The Exception Syndrome Register .1, 2, 3
FAR_ELnFault Address RegisterHolds the virtual faulting address. See Handling synchronous exceptions.1, 2, 3
FPCRFloating-point Control RegisterControls floating-point extension behavior. The fields in this register map to the equivalent fields in the AArch32 FPSCR. See New features for NEON and Floating-point in AArch64.-
FPSRFloating-point Status RegisterProvides floating-point system status information. The fields in this register map to the equivalent fields in the AArch32 FPSCR. See New features for NEON and Floating-point in AArch64.-
HCR_ELnHypervisor Configuration RegisterControls virtualization settings and trapping of exceptions to EL2. See Exception handling.2
MAIR_ELnMemory Attribute Indirection RegisterProvides the memory attribute encodings corresponding to the possible values in a Long-descriptor format translation table entry for stage 1 translations at ELn. See Memory types.1, 2, 3
MIDR_ELnMain ID RegisterThe type of processor the code is running on (part number and revision).1
MPIDR_ELnMultiprocessor Affinity RegisterThe processor and cluster IDs, in multi-core or cluster systems. See Determining which core the code is running on.1
SCR_ELnSecure Configuration RegisterControls Secure state and trapping of exceptions to EL3. See Handling synchronous exceptions.3
SCTLR_ELnSystem Control RegisterControls architectural features, for example the MMU, caches and alignment checking.0, 1, 2, 3
SPSR_ELnSaved Program Status RegisterHolds the saved processor state when an exception is taken to this mode or Exception level.abt, fiq, irq, und, 1,2, 3
TCR_ELnTranslation Control RegisterDetermines which of the Translation Table Base Registers define the base address for a translation table walk required for the stage 1 translation of a memory access from ELn. Also controls the translation table format and holds cacheability and shareability information. See Separation of kernel and application Virtual Address spaces.1, 2, 3
TPIDR_ELnUser Read/Write Thread ID RegisterProvides a location where software executing at ELn can store thread identifying information, for OS management purposes. See Context switching.0, 1, 2, 3
TPIDRRO_ELnUser Read-Only Thread ID RegisterProvides a location where software executing at EL1 or higher can store thread identifying information. This informaton is visible to software executing at EL0, for OS management purposes. See Context switching.0
TTBR0_ELnTranslation Table Base Register 0Holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses at ELn. See Separation of kernel and application Virtual Address spaces.1, 2, 3
TTBR1_ELnTranslation Table Base Register 1Holds the base address of translation table 1, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses at EL0 and EL1. See Separation of kernel and application Virtual Address spaces.1
VBAR_ELnVector Based Address RegisterHolds the exception base address for any exception that is taken to ELn. See AArch64 exception table.1, 2, 3
VTCR_ELnVirtualization Translation Control RegisterControls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1. Also holds cacheability and shareability information for the accesses. See Translations at EL2 and EL3.2
VTTBR_ELnVirtualization Translation Table Base RegisterHolds the base address of the translation table for the stage 2 translation of memory accesses from Non-secure EL0 and EL1. See Memory translation.2

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