4.1.5. Saved Process Status Register

When taking an exception, the processor state is stored in the relevant Saved Program Status Register (SPSR), in a similar way to the CPSR in ARMv7. The SPSR holds the value of PSTATE before taking an exception and is used to restore the value of PSTATE when executing an exception return.

Figure 4.4. SPSR

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The individual bits represent the following values for AArch64:

N

Negative result (N flag).

Z

Zero result (Z) flag.

C

Carry out (C flag).

V

Overflow (V flag).

SS

Software Step. Indicates whether software step was enabled when an exception was taken.

IL

Illegal Execution State bit. Shows the value of PSTATE.IL immediately before the exception was taken.

D

Process state Debug mask. Indicates whether debug exceptions from watchpoint, breakpoint, and software step debug events that are targeted at the Exception level the exception occurred in were masked or not.

A

SError (System Error) mask bit.

I

IRQ mask bit.

F

FIQ mask bit.

M[4]

Execution state that the exception was taken from. A value of 0 indicates AArch64.

M[3:0]

Mode or Exception level that an exception was taken from.

In ARMv8, the SPSR written to depends on the Exception level. If the exception is taken in EL1, then SPSR_EL1 is used. If the exception is taken in EL2, then SPSR_EL2 is used, and if the exception is taken in EL3, SPSR_EL3 is used. The core populates the SPSR when taking an exception.

Note

The register pairs ELR_ELn and SPSR_ELn that are associated with an Exception level retain their state during execution at a lower Exception level.

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