4.2. Processor state

AArch64 does not have a direct equivalent of the ARMv7 Current Program Status Register (CPSR). In AArch64, the components of the traditional CPSR are supplied as fields that can be made accessible independently. These are referred to collectively as Processor State (PSTATE).

The Processor State, or PSTATE fields, for AArch64 have the following definitions:

Table 4.4. PSTATE field definitions

NameDescription
NNegative condition flag.
ZZero condition flag.
CCarry condition flag.
VoVerflow condition flag.
DDebug mask bit.
ASError mask bit.
IIRQ mask bit.
FFIQ mask bit.
SS

Software Step bit.

IL

Illegal execution state bit.

EL (2)Exception level.
nRW

Execution state

0 = 64-bit

1 = 32-bit

SP

Stack Pointer selector.

0 = SP_EL0

1 = SP_ELn


In AArch64, you return from an exception by executing the ERET instruction, and this causes the SPSR_ELn to be copied into PSTATE. This restores the ALU flags, execution state, Exception level, and the processor branches. From here, you continue execution from the address in ELR_ELn.

The PSTATE.{N, Z, C, V} fields can be accessed at EL0. All other PSTATE fields can be executed at EL1 or higher and are undefined at EL0.

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