6.2.5. Conditional instructions

The A64 instruction set does not support conditional execution for every instruction. Predicated execution of instructions does not offer sufficient benefit to justify its significant use of opcode space.

Processor state, describes the four status flags, Zero (Z), Negative (N), Carry (C) and Overflow (V). Table 6.4 indicates the value of these bits for flag setting operations.

Table 6.4. Condition flag

NNegativeSet to the same value as bit[31] of the result. For a 32-bit signed integer, bit[31] being set indicates that the value is negative.
ZZeroSet to 1 if the result is zero, otherwise it is set to 0.
CCarrySet to the carry-out value from result, or to the value of the last bit shifted out from a shift operation.
VOverflowSet to 1 if signed overflow or underflow occurred, otherwise it is set to 0.

The C flag is set if the result of an unsigned operation overflows the result register.

The V flag operates in the same way as the C flag, but for signed operations.


The condition flags (NZCV) and the condition codes are the same as in A32 and T32. However, A64 adds NV (0b1111), though it behaves the same as its complement, AL (0b1110). This differs from A32, which did not assign any meaning to 0b1111.

Table 6.5. Condition codes

Code EncodingMeaning (when set by CMP) Meaning (when set by FCMP) Condition flags
EQ 0b0000Equal to.Equal to. Z =1
NE 0b0001Not equal to. Unordered, or not equal to. Z = 0
CS0b0010Carry set (identical to HS).Greater than, equal to, or unordered (identical to HS).C = 1
HS0b0010Greater than, equal to (unsigned) (identical to CS).Greater than, equal to, or unordered (identical to CS).C = 1
CC0b0011Carry clear (identical to LO).Less than (identical to LO).C = 0
LO0b0011Unsigned less than (identical to CC).Less than (identical to CC).C = 0
MI 0b0100Minus, Negative. Less than. N = 1
PL 0b0101Positive or zero. Greater than, equal to, or unordered. N = 0
VS 0b0110Signed overflow. Unordered. (At least one argument was NaN). V = 1
VC 0b0111No signed overflow. Not unordered. (No argument was NaN). V = 0
HI 0b1000Greater than (unsigned). Greater than or unordered. (C = 1) && (Z = 0)
LS 0b1001Less than or equal to (unsigned). Less than or equal to. (C = 0) || (Z = 1)
GE 0b1010Greater than or equal to (signed). Greater than or equal to. N==V
LT 0b1011Less than (signed). Less than or unordered. N!=V
GT 0b1100Greater than (signed). Greater than. (Z==0) && (N==V)
LE 0b1101Less than or equal to (signed). Less than, equal to or unordered. (Z==1) || (N!=V)
AL0b1110Always executed. Default. Always executed. Any
NV0b1111Always executed.Always executed.Any

There are a small set of conditional data processing instructions. These instructions are unconditionally executed but use the condition flags as an extra input to the instruction. This set has been provided to replace common usage of conditional execution in ARM code.

The instructions types which read the condition flags are:

Add/subtract with carry

The traditional ARM instructions, for example, for multi-precision arithmetic and checksums.

Conditional select with optional increment, negate, or invert

Conditionally select between one source register and a second incremented, negated, inverted, or unmodified source register.

These are the most common uses of single conditional instructions in A32 and T32. Typical uses include conditional counting or calculating the absolute value of a signed quantity.

Conditional operations

The A64 instruction set enables conditional execution of only program flow control branch instructions. This is in contrast to A32 and T32 where most instructions can be predicated with a condition code. These can be summarized as follows:

Conditional select (move)
  • CSEL Select between two registers based on a condition. Unconditional instructions, followed by a conditional select, can replace short conditional sequences.

  • CSINC Select between two registers based on a condition. Return the first source register or the second source register incremented by one.

  • CSINV Select between two registers based on a condition. Return the first source register or the inverted second source register.

  • CSNEG Select between two registers based on a condition. Return the first source register or the negated second source register.

Conditional set

Conditionally select between 0 and 1 (CSET) or 0 and -1 (CSETM). Used, for example, to set the condition flags as a boolean value or mask in a general register.

Conditional compare

(CMP and CMN) Sets the condition flags to the result of a comparison if the original condition is true. If not true, the conditional flags are set to a specified condition flag state. The conditional compare instruction is very useful for expressing nested or compound comparisons.


Conditional select and conditional compare are also available for floating-point registers using the FCSEL and FCCMP instructions.

For example:

  CSINC X0, X1, X0, NE  // Set the return register X0 to X1 if Zero flag clear,
                        // else increment X0

Some aliases to the example instructions are provided, where either the zero register is used, or the same register is used as both destination and both source registers for the instruction.

For example:

  CINC X0, X0, LS           // If less than or same (LS) then X0 = X0 + 1
  CSET W0, EQ               // If the previous comparison was equal (Z=1) then W0 = 1, 
                            // else W0 = 0
  CSETM X0, NE              // If not equal then X0 = -1, else X0 = 0 

This class of instructions provides a powerful way to avoid the use of branches or conditionally executed instructions. Compilers, or assembly programmers, might adopt a technique of performing the operations for both branches of an if-then-else statement. Then the correct result is selected at the end.

For example, consider the simple C code:

  if (i == 0)  r = r + 2;  else  r = r - 1;

This might produce code similar to:

  CMP w0, #0            // if (i == 0)
  SUB w2, w1, #1        // r = r - 1
  ADD w1, w1, #2        // r = r + 2
  CSEL w1, w1, w2, EQ   // select between the two results
Copyright © 2015 ARM. All rights reserved.ARM DEN0024A