16.2.2. CPU migration

In this model, each big core is paired with a LITTLE core. Only one core in each pair is active at any one time, with the inactive core being powered down. The active core in the pair is chosen according to current load conditions. Using the example in Figure 16.2, the operating system sees four logical cores. Each logical core can physically be a big or LITTLE core. This choice is driven by Dynamic Voltage and Frequency Scaling (DVFS). This model requires the same number of cores in both the clusters.

Figure 16.2. CPU migration

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The system actively monitors the load on each core. High load causes the execution context to be moved to the big core, and conversely, when the load is low, the execution is moved to the LITTLE core. Only one core in the pairing can be active at any time. When the load is moved from an outbound core (the core the load leaves) to an inbound core (the core it arrives at), the former is switched off. This model allows a mix of big and LITTLE cores to be active at any one time.

Copyright © 2015 ARM. All rights reserved.ARM DEN0024A
Non-ConfidentialID050815