11.6. Cache discovery

Cache maintenance operations can be performed either by cache set, or way, or by Virtual Address. Code that is platform-independent might need to know the size of a cache, the size of the cache lines, numbers of sets and ways, and how many levels of cache there are in the system. This requirement is most likely to arise for post-reset cache invalidation and zero operations. All other operations on architectural caches are likely to be made on a PoC or PoU basis.

There are a number of system control registers that contain this information:.

Exception level accesses to two separate registers are required to determine the number of sets and ways in a cache.

  1. Code must first write to the Cache Size Selection Register (CSSELR_EL1) to select which cache you want the information for.

  2. Code then reads the Cache Size ID Register (CCSIDR/CCSIDR_EL1).

  3. The Data cache Zero ID Register (DCZID_EL0) contains the block size to be zeroed for Zero operations.

  4. The [DZE] bit of the SCTLR/SCTLR_EL1 and the [TDZ] bit in the Hypervisor Configuration Register (HCR/HCR_EL2) control which execution levels and which worlds can access DCZID_EL0. CLIDR_EL1, CSSELR_EL1, and CCSIDR_EL1 are only accessible via privileged code, that is, PL1 or higher in AArch32, or EL1 or higher in AArch64.

  5. If execution of the Data Cache Zero by Virtual Address (DC ZVA) instruction is prohibited at an Exception level, as controlled for EL0 by the SCTLR_EL1.DZE bit, and for Non-secure execution in EL1 and EL0 by the HCR_EL2.TDZ bit, then reading this register returns a value that indicates that the instruction is not supported.

  6. The CLIDR register is only aware of how many levels of cache are integrated into the processor itself. It cannot provide information about any caches in the external memory system.

    For example, if only L1 and L2 are integrated, CLIDR/CLIDR_EL1 identifies two levels of cache and the processor is unaware of any external L3 cache.

    It might be necessary to take into account non-integrated caches when performing cache maintenance, or code that is maintaining coherency with integrated caches.

    Figure 11.13. 

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    In addition, in a big.LITTLE system, the described cache hierarchy can differ from core to core, for example, the Cortex-A53 and Cortex-A57 processors have different CTR.L1IP fields.

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