12.3.2. Configuring and enabling the MMU

Writes to the system registers controlling the MMU are context-changing events and there are no ordering requirements between them. The results of these events are not guaranteed to be seen until a context synchronization event (See Barriers).

  MSR TTBR0_EL1, X0               // Set TTBR0
  MSR TTBR1_EL1, X1               // Set TTBR1
  MSR TCR_EL1, X2                 // Set TCR
  ISB                             // The ISB forces these changes to be seen before /
                                  // the MMU is enabled.
  MRS X0, SCTLR_EL1               // Read System Control Register configuration data
  ORR X0, X0, #1                  	// Set [M] bit and enable the MMU.
  MSR SCTLR_EL1, X0               // Write System Control Register configuration data
  ISB                             // The ISB forces these changes to be seen by the /
                                  // next instruction

This is aside from the requirement for flat mapping, which is to make sure we know which instruction is executed directly after the write to SCTLR_EL1.M. If we see the result of the write it is the instruction at VA+4 using the new translation regime. If we don’t see the result it is still the instruction at VA+4 but where the VA = PA. The ISB doesn't help here as we cannot guarantee it is the next instruction executed unless we flat map.

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