6.3.4. Specifying the address for a Load or Store instruction

The addressing modes available to A64 are similar to those in A32 and T32. There are some additional restrictions as well as some new features, but the addressing modes available to A64 will not be surprising to someone familiar with A32 or T32.

In A64, the base register of an address operand must always be an X register. However, several instructions support zero-extension or sign-extension so that a 32-bit offset can be provided as a W register.

Offset modes

Offset addressing modes add an immediate value or an optionally-modified register value to a 64-bit base register to generate an address.

Table 6.8. Offset addressing modes

Example instructionDescription
LDR X0, [X1] Load from the address in X1
LDR X0, [X1, #8] Load from address X1 + 8
LDR X0, [X1, X2]Load from address X1 + X2
LDR X0, [X1, X2, LSL, #3] Load from address X1 + (X2 << 3)
LDR X0, [X1, W2, SXTW]Load from address X1 + sign_extend(W2)
LDR X0, [X1, W2, SXTW, #3] Load from address X1 + (sign_extend(W2) << 3)

Typically, when specifying a shift or extension option, the shift amount can be either 0 (the default) or log2 of the access size in bytes (so that Rn << <shift> multiplies Rn by the access size). This supports common array-indexing operations.

  // A C example showing accesses that a compiler is likely to generate.
  void example_dup(int32_t a[], int32_t length) {
    int32_t first = a[0];                             // LDR W3, [X0]
    for (int32_t i = 1; i < length; i++) {
    a[i] = first;                                     // STR W3, [X0, W2, SXTW, #2]
    }  }

Index modes

Index modes are similar to offset modes, but they also update the base register. The syntax is the same as in A32 and T32, but the set of operations is more restrictive. Usually, only immediate offsets can be provided for index modes.

There are two variants: pre-index modes which apply the offset before accessing the memory, and post-index modes which apply the offset after accessing the memory.

Table 6.9. Index addressing modes

Example instructionDescription
LDR X0, [X1, #8]! Pre-index: Update X1 first (to X1 + #8), then load from the new address
LDR X0, [X1], #8 Post-index: Load from the unmodified address in X1 first, then update X1 (to X1 + #8)
STP X0, X1, [SP, #-16]! Push X0 and X1 to the stack.
LDP X0, X1, [SP], #16 Pop X0 and X1 off the stack.

These options map cleanly onto some common C operations:

  // A C example showing accesses that a compiler is likely to generate.
  void example_strcpy(char * dst, const char * src) 
  char c;
  do {
      c = *(src++);             // LDRB W2, [X1], #1
      *(dst++) = c;             // STRB W2, [X0], #1
      } while (c != '\0');

PC-relative modes (load-literal)

A64 adds another addressing mode specifically for accessing literal pools. Literal pools are blocks of data encoded in an instruction stream. The pools are not executed, but their data can be accessed from surrounding code using PC-relative memory addresses. Literal pools are often used to encode constant values that do not fit into a simple move-immediate instruction.

In A32 and T32, the PC can be read like a general-purpose register, so a literal pool can be accessed simply by specifying PC as the base register.

In A64, PC is not generally accessible, but instead there is a special addressing mode (for load instructions only) that accesses a PC-relative address. This special-purpose addressing mode also has a much greater range than the PC-relative loads in A32 and T32 could achieve, so literal pools can be positioned more sparsely.

Table 6.10. 

Example instructionDescription
LDR W0, <label> Load 4 bytes from <label> into W0
LDR X0, <label>Load 8 bytes from <label> into X0
LDRSW X0, <label> Load 4 bytes from <label> and sign-extend into X0
LDR S0, <label> Load 4 bytes from <label> into S0
LDR D0, <label> Load 8 bytes from <label> into D0
LDR Q0, <label> Load 16 bytes from <label> into Q0


<label> must be 4-byte-aligned for all variants.

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