3.2. Changing Exception levels

In the ARMv7 architecture, the processor mode can change under privileged software control or automatically when taking an exception. When an exception occurs, the core saves the current execution state and the return address, enters the required mode, and possibly disables hardware interrupts.

This is summarized in the following table. Applications operate at the lowest level of privilege, PL0, previously unprivileged mode. Operating systems run at PL1, and the Hypervisor in a system with the Virtualization extensions at PL2. The Secure monitor, which acts as a gateway for moving between the Secure and Non-secure (Normal) worlds, also operates at PL1.

Table 3.1. ARMv7 processor modes

ModeFunction

Security

state

Privilege

level

User (USR)Unprivileged mode in which most applications run BothPL0
FIQEntered on an FIQ interrupt exceptionBoth

PL1

IRQEntered on an IRQ interrupt exceptionBothPL1

Supervisor

(SVC)

Entered on reset or when a Supervisor Call instruction (SVC) is executedBothPL1
Monitor (MON)

Entered when the SMC instruction (Secure Monitor Call) is executed or when the processor takes an exception which is configured for secure handling.

Provided to support switching between Secure and Non-secure states.

Secure onlyPL1
Abort (ABT)Entered on a memory access exceptionBothPL1
Undef (UND)Entered when an undefined instruction is executedBothPL1
System (SYS)Privileged mode, sharing the register view with User modeBothPL1
Hyp (HYP)

Entered by the Hypervisor Call and Hyp Trap exceptions.

Non-secure onlyPL2

Figure 3.5. ARMv7 privilege levels

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In AArch64, the processor modes are mapped onto the Exception levels as in Figure 3.6. As in ARMv7 (AArch32) when an exception is taken, the processor changes to the Exception level (mode) that supports the handling of the exception.

Figure 3.6. AArch32 processor modes

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Movement between Exception levels follows these rules:

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