4.1. AArch64 special registers

In addition to the 31 core registers, there are also several special registers.

Figure 4.3. AArch64 special registers

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Note

There is no register called X31 or W31. Many instructions are encoded such that the number 31 represents the zero register, ZR (WZR/XZR). There is also a restricted group of instructions where one or more of the arguments are encoded such that number 31 represents the Stack Pointer (SP).

When accessing the zero register, all writes are ignored and all reads return 0. Note that the 64-bit form of the SP register does not use an X prefix.

Table 4.1. Special registers in AArch64

NameSizeDescription
WZR32 bitsZero register
XZR64 bitsZero register
WSP32 bitsCurrent stack pointer
SP64 bitsCurrent stack pointer
PC64 bitsProgram counter

In the ARMv8 architecture, when executing in AArch64, the exception return state is held in the following dedicated registers for each Exception level:

There is a dedicated SP per Exception level, but it is not used to hold return state.

Table 4.2. Special registers by Exception level

 EL0EL1EL2EL3
Stack Pointer (SP)SP_EL0SP_EL1SP_EL2SP_EL3
Exception Link Register (ELR)  ELR_EL1ELR_EL2ELR_EL3
Saved Process Status Register (SPSR) SPSR_EL1SPSR_EL2SPSR_EL3

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