4.6.1. Floating-point register organization in AArch64

In NEON and floating-point instructions that operate on scalar data, the floating-point and NEON registers behave similarly to the main general-purpose integer registers. Therefore, only the lower bits are accessed, with the unused high bits ignored on a read and set to zero on a write. The qualified names for scalar floating-point and NEON names indicate the number of significant bits as follows, where n is a register number 0-31.

Table 4.7. Operand name for differently sized floats

PrecisionSize (bits)Name
Half16Hn
Single32Sn
Double64Dn

Figure 4.10. Arrangement of floating-point values

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Note

16-bit floating-point is supported, but only as a format to be converted from or to. It is not supported for data processing operations.

The F prefix and the float size is specified by the floating-point ADD instruction:

  FADD Sd, Sn, Sm  // Single-precision
  FADD Dd, Dn, Dm  // Double-precision

The half-precision floating-point instructions are for converting between different sizes:

  FCVT Sd, Hn  // half-precision to single-precision
  FCVT Dd, Hn  // half-precision to double-precision
  FCVT Hd, Sn  // single-precision to half-precision
  FCVT Hd, Dn  // double-precision to half-precision
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