4.6.2. Scalar register sizes

In AArch64, the mapping for the integer scalars has changed from what is used in ARMv7-A to the mapping shown in Figure 4.11:

Figure 4.11. Arrangement of ARMv8 registers when holding scalar values

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In Figure 4.11 S0 is the bottom half of D0, which is the bottom half of Q0. S1 is the bottom half of D1, which is the bottom half of Q1, and so on. This eliminates many of the problems compilers have in auto-vectorizing high-level code.

Note

Only the bottom bits of each register set are used in each case. The rest of the register space is ignored when read, and filled with zeros when written.

A consequence of this mapping is that if a program executing in AArch64 is interpreting D or S registers from AArch32 execution. Then the program must unpack the D or S registers from the V registers before using them.

For the scalar ADD instruction:

  ADD Vd, Vn, Vm

If the size was, for example, 32 bits, the instruction would be:

  ADD Sd, Sn, Sm

Table 4.8. Operand name for differently sized scalars

Word sizeSize (bits)Name
Byte8Bn
Halfword16Hn
Word32Sn
Doubleword64Dn
Quadword128Qn

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