4.6.3. Vector register sizes

Vectors can be 64-bits wide with one or more elements or 128-bits wide with two or more elements as shown in Figure 4.12:

Figure 4.12. Vector sizes

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For the vector ADD instruction:

 ADD Vd.T, Vn.T, Vm.T

For 32-bit vectors this time, with 4 lanes, the instruction becomes:

 ADD Vd.4S, Vn.4S, Vm.4S

Table 4.9. Operand names for different size vectors

NameShape
Vn.8B8 lanes, each containing an 8-bit element
Vn.16B16 lanes, each containing an 8-bit element
Vn.4H4 lanes, each containing a 16-bit element
Vn.8H8 lanes, each containing a 16-bit element
Vn.2S2 lanes, each containing a 32-bit element
Vn.4S4 lanes, each containing a 32-bit element
Vn.1D1 lane containing a 64-bit element
Vn.2D2 lanes, each containing a 64-bit element

When these registers are used in a specific instruction form, the names must be further qualified to indicate the data shape. More specifically, this means the data element size and the number of elements or lanes held within them.

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