6.2.4. Bitfield and byte manipulation instructions

There are instructions that extend a byte, halfword, or word to register size, which can be either X or W. These instructions exist in both signed (SXTB, SXTH, SXTW) and unsigned (UXTB, UXTH) variants and are aliases to the appropriate bitfield manipulation instruction.

Both the signed and unsigned variants of these instructions extend a byte, halfword, or word (although only SXTW operates on a word) to register size. The source is always a W register. The destination register is either an X or a W register, except for SXTW which must be an X register.

For example:

  SXTB X0, W1        // Sign extend the least significant byte of register W1 
                     // from 8-bits to 64-bit by repeating the leftmost bit of the
                     // byte.

Bitfield instructions are similar to those that exist in ARMv7 and include Bit Field Insert (BFI), and signed and unsigned Bit Field Extract ((S/U)BFX). There are extra bitfield instructions too, such as BFXIL (Bit Field Extract and Insert Low), UBFIZ (Unsigned Bit Field Insert in Zero), and SBFIZ (Signed Bit Field Insert in Zero).

Figure 6.2. Bit manipulation instructions

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There are also BFM, UBFM, and SBFM instructions. These are Bit Field Move instructions, which are new for ARMv8. However, the instructions do not need to be used explicitly, as aliases are provided for all cases. These aliases are the bitfield operations already described: [SU]XT[BHWX], ASR/LSL/LSR immediate, BFI, BFXIL, SBFIZ, SBFX, UBFIZ, and UBFX.

If you are familiar with the ARMv7 architecture, you might recognize the other bit manipulation instruction:

Similarly, the same byte manipulation instructions:

These operations can be performed on either word (32-bit) or doubleword (64-bit) sized registers, except for REV32, which applies only to 64-bit registers.

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