6.3.3. Floating-point and NEON scalar loads and stores

Load and Store instructions can also access floating-point/NEON registers. Here, the size is determined only by the register being loaded or stored, which can be any of the B, H, S, D, or Q registers. This information is summarized in Table 6.6Table 6.6, and Table 6.7.

For Load instructions:

Table 6.6. Memory bits written by Load instructions

LoadXtWtQtDtStHtBt
LDR64321286432169
LDP1286425612864--
LDRB-8-----
LDRH-16-----
LDRSB88-----
LDRSH1616-----
LDRSW32------
LDPSW-------

For Store instructions:

Table 6.7. Memory bits read by Store instructions

StoreXtWtQtDtStHtBt
STR64321266432168
STP1286425612864--
STRB-8-----
STRH-16-----

No sign-extension options are available for loads into FP/SIMD registers. Addresses for such loads are still specified using the general-purpose registers.

For example:

  LDR D0, [X0, X1]

Loads register D0 with the doubleword at the memory address pointed to by X0 plus X1.

Note

Floating-point and scalar NEON Loads and Stores use the same addressing modes as integer Loads and Stores.

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