6.3.5. Accessing multiple memory locations

A64 does not include the Load Multiple (LDM) or Store Multiple (STM) instructions that are available to A32 and T32 code.

In A64 code, there are the Load Pair (LDP) and Store Pair (STP) instructions. Unlike the A32 LDRD and STRD instructions, any two integer registers can be read or written. Data is read or written to or from adjacent memory locations. The addressing mode options provided for these instructions are more restrictive than for other memory access instructions. LDP and STP instructions can only use a base register with a scaled 7-bit signed immediate value, with optional pre- or post-increment. Unaligned accesses are possible for LDP and STP, unlike the 32-bit LDRD and STRD.

Table 6.11. Register Load/Store pair

Load and Store pairDescription
LDP W3, W7, [X0]Loads word at address X0 into W3 and word at address X0 + 4 into W7. See Figure 6.6.
LDP X8, X2, [X0, #0x10]!Loads doubleword at address X0 + 0x10 into X8 and the doubleword at address X0 + 0x10 + 8 into X2 and add 0x10 to X0. See Figure 6.7.
LDPSW X3, X4, [X0]Loads word at address X0 into X3 and word at address X0 + 4 into X4, and sign extends both to doubleword size.
LDP D8, D2, [X11], #0x10Loads doubleword at address X11 into D8 and the doubleword at address X11 + 8 into D2 and adds 0x10 to X11.
STP X9, X8, [X4]Stores the doubleword in X9 to address X4 and stores the doubleword in X8 to address X4 + 8.

Figure 6.6. LDP W3, W7 [X0]

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Figure 6.7. LDP X8, X2, [X0 + #0x10]!

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