11.3. Cache policies

The cache policies enable us to describe when a line should be allocated to the data cache and what should happen when a store instruction is executed that hits in the data cache.

The cache allocation policies are:

Write allocation (WA)

A cache line is allocated on a write miss. This means that executing a store instruction on the processor might cause a burst read to occur. There is a linefill to obtain the data for the cache line, before the write is performed. The cache contains the whole line, which is its smallest loadable unit, even if you are only writing to a single byte within the line.

Read allocation (RA)

A cache line is allocated on a read miss.

The cache update policies are:

Write-back (WB)

A write updates the cache only and marks the cache line as dirty. External memory is updated only when the line is evicted or explicitly cleaned.

Figure 11.8. Write-back

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Write-through (WT)

A write updates both the cache and the external memory system. This does not mark the cache line as dirty.

Figure 11.9. Write-through

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Data reads which hit in the cache behave the same in both WT and WB cache modes.

The cacheable properties of normal memory are specified separately as inner and outer attributes. The divide between inner and outer is implementation defined and is covered in greater detail in Chapter 13. Typically, inner attributes are used by the integrated caches, and outer attributes are made available on the processor memory bus for use by external caches.

Figure 11.10. Cacheable properties of memory

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Normal memory can be speculatively accessed by the processor and this means that it can potentially automatically load data into the cache without the programmer having explicitly requested a specific address. This is covered in more detail in Chapter 13 Memory Ordering. However, it is also possible for the programmer to give an indication to the core about which data is used in the future. The ARMv8-A provides preload hint instructions. It is implementation defined whether the caches support speculation and preload. The following instructions are available:

More generally, the A64 instruction to prefetch memory has the following form:

PRFM <prfop>, addr 

Where:

<prfop>
<type><target><policy> | #uimm5
<type>

PLD for prefetch for load

PST for prefetch for store

<target>

L1 for L1 cache, L2 for L2 cache, L3 for L3 cache

<policy>

KEEP for retain or temporal prefetch means allocate in cache normally

STRM for streaming or non-temporal prefetch means the memory is used only once

uimm5

Represents the hint encodings as a 5-bit immediate. These are optional.

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