11.4. Point of coherency and unification

For set-based and way-based clean and invalidate, the operation is performed on a specific level of cache. For operations that use a Virtual Address, the architecture defines two points:

Knowledge of the PoU enables self-modifying code to ensure future instruction fetches are correctly made from the modified version of the code. They can do this by using a two-stage process:

The ARM architecture does not require the hardware to ensure coherency between instruction caches and memory, even for locations of shared memory.

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