12.4.3. Cache configuration

The MMU uses translation tables and translation registers to control which memory locations are cacheable. The MMU controls the cache policy, memory attributes, and access permissions, and provides Virtual to Physical Address translation.

Figure 12.14. Memory busses and caches

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Software configuration is performed by system registers (some of which are listed in Chapter 4 ARMv8 Registers.)

In some designs, the external memory system might contain further implementation-specific caches of external memories.

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