12.4.4. Cache policies

The MMU translation tables also define the cache policy for each block within the memory system. Memory regions that are defined as Normal might be marked as cacheable or non-cacheable. Bits [4:2] from the translation table entry refer to one of the eight memory attribute encodings in the Memory Attribute Indirection Register (MAIR). The memory attribute encodings then specify the cache policies to use when accessing that memory. These are hints to the processor and it is implementation defined whether all cache policies are supported in a particular implementation and which cache data is regarded as coherent. A memory region can be defined in terms of its shareability property.

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