19.3.11. Compatibility with VE model and platform

Software that ran on the previous VE model should be compatible with the AEMv8-A Base Platform FVP, but might require changes to the following configuration options:


The AEMv8-A Base Platform FVP uses GICv3 by default. It can be configured to use GICv2 or GICv2m compatibility modes.

To configure the model as GICv2m, set the following:

  -C gicv3.gicv2-only=1                          \
  -C cluster0.gic.GICD-offset=0x10000            \
  -C cluster0.gic.GICC-offset=0x2F000            \
  -C cluster0.gic.GICH-offset=0x4F000            \
  -C cluster0.gic.GICH-other-CPU-offset=0x50000  \
  -C cluster0.gic.GICV-offset=0x6F000            \
  -C cluster0.gic.PERIPH-size=0x80000            \
  -C cluster1.gic.GICD-offset=0x10000            \
  -C cluster1.gic.GICC-offset=0x2F000            \
  -C cluster1.gic.GICH-offset=0x4F000            \
  -C cluster1.gic.GICH-other-CPU-offset=0x50000  \
  -C cluster1.gic.GICV-offset=0x6F000            \
  -C cluster1.gic.PERIPH-size=0x80000            \
  -C gic_distributor.GICD-alias=0x2c010000

To configure the model as GICv2, set the following:

  -C gicv3.gicv2-only=1                         \
  -C cluster0.gic.GICD-offset=0x1000            \
  -C cluster0.gic.GICC-offset=0x2000            \
  -C cluster0.gic.GICH-offset=0x4000            \
  -C cluster0.gic.GICH-other-CPU-offset=0x5000  \
  -C cluster0.gic.GICV-offset=0x6000            \
  -C cluster0.gic.PERIPH-size=0x8000            \
  -C cluster1.gic.GICD-offset=0x1000            \
  -C cluster1.gic.GICC-offset=0x2000            \
  -C cluster1.gic.GICH-offset=0x4000            \
  -C cluster1.gic.GICH-other-CPU-offset=0x5000  \
  -C cluster1.gic.GICV-offset=0x6000            \
  -C cluster1.gic.PERIPH-size=0x8000            \
  -C gic_distributor.GICD-alias=0x2c010000

To configure MSI frames for GICv2m, extra parameters are available to set the base address and configuration of each of 16 possible frames, eight Secure and eight Non-secure:

  -C gic_distributor.MSI_S-frame0-base=ADDRESS  \
  -C gic_distributor.MSI_S-frame0-min-SPI=NUM   \
  -C gic_distributor.MSI_S-frame0-max-SPI=NUM

In this example, you can replace MSI_S with MSI_NS, for NS frames, and you can replace frame0 with frame1 to frame7 for each of the possible 16 frames. If the base address is not specified for a given frame, or the SPI numbers are out of range, the corresponding frame is not instantiated.


The AEMv8-A core model includes an implementation of the GICv3 system registers. This is enabled by default.

The GIC distributor and CPU interface have several parameters to allow configuration of the model to match different implementation options. Use --list-params to get a full list. Configuration options for the GIC model should be available under:

  • cpu/cluster.gic.*

  • cpu/cluster.gicv3.*

  • gic_distributor.*

System global counter

The VE model did not provide a memory-mapped interface to the system global counter, and enabled the free-running timer from reset. However, the architectural requirement is that such a counter is not enabled at reset. This means that the Generic Timer registers of the cores do not operate unless either:

  • Software enables the counter peripheral by writing the FCREQ[0] and EN bits in CNTCR at 0x2a43000. This is the preferred approach.

  • The -C bp.refcounter.non_arch_start_at_default=1 parameter is set. This is a backup approach for compatibility with older software.

Disable platform security

The VE model optionally restricted accesses according to a fixed security map. In the AEMv8-A Base Platform FVP, the security map for peripherals is enhanced and is now enabled by default. Software must program the TZC-400 to make any accesses to DRAM, because all accesses are blocked in the reset configuration.

For compatibility with software that has not been updated to program the TZC-400, the following parameter is provided, and this causes all accesses to be permitted regardless of security state:

  -C bp.secure_memory=false
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