Glossary

Abbreviations and terms used in this document are defined here.

AAPCS

ARM Architecture Procedure Call Standard.

AArch32 state

The ARM 32-bit execution state that uses 32-bit general-purpose registers, and a 32-bit Program Counter (PC), Stack Pointer (SP), and Link Register (LR). AArch32 execution state provides a choice of two instruction sets, A32 and T32, previously called the ARM and Thumb instruction sets.

AArch64 state

The ARM 64-bit execution state that uses 64-bit general-purpose registers, and a 64-bit Program Counter (PC), Stack Pointer (SP), and Exception Link Registers (ELR). AArch64 execution state provides a single instruction set, A64.

ABI

Application Binary Interface.

ACE

AXI Coherency Extensions.

AES

Advanced Encryption Standard.

AMBA®

Advanced Microcontroller Bus Architecture.

AMP

Asymmetric Multi-Processing.

ARM ARM

The ARM Architecture Reference Manual.

ASIC

Application Specific Integrated Circuit.

ASID

Address Space ID.

AXI

Advanced eXtensible Interface.

BE8

Byte Invariant Big-Endian Mode.

BTAC

Branch Target Address Cache.

BTB

Branch Target Buffer.

CCI

Cache Coherent Interface.

CHI

Coherent Hub Interface.

CP15

Coprocessor 15 for AArch32 and ARMv7-A- System control coprocessor.

DAP

Debug Access Port.

DMA

Direct Memory Access.

DMB

Data Memory Barrier.

DS-5

The ARM Development Studio.

DSB

Data Synchronization Barrier.

DSP

Digital Signal Processing.

DSTREAM

An ARM debug and trace unit.

DVFS

Dynamic Voltage/Frequency Scaling.

EABI

Embedded ABI.

ECC

Error Correcting Code.

ECT

Embedded Cross Trigger.

EL0

Exception level used to execute user applications.

EL1

Exception level normally used to run operating systems.

EL2

Hypervisor Exception level. In the Normal world, or Non-Secure state, this is used to execute hypervisor code.

EL3

Secure Monitor exception level.This is used to execute the code that guards transitions between the Secure and Normal worlds.

ETB

Embedded Trace Buffer™.

ETM

Embedded Trace Macrocell™.

Execution state

The operational state of the processor, either 64-bit (AArch64) or 32-bit (AArch32).

FIQ

An interrupt type (formerly fast interrupt).

FPSCR

Floating-Point Status and Control Register.

GCC

GNU Compiler Collection.

GIC

Generic Interrupt Controller.

Harvard architecture

Architecture with physically separate storage and signal pathways for instructions and data.

HCR

Hyp Configuration Register.

HMP

Heterogenous Multi-Processing.

IMPLEMENTATION DEFINED

Some properties of the processor are defined by the manufacturer.

IPA

Intermediate Physical Address.

IRQ

Interrupt Request, normally for external interrupts.

ISA

Instruction Set Architecture.

ISB

Instruction Synchronization Barrier.

ISR

Interrupt Service Routine.

Jazelle

The ARM bytecode acceleration technology.

LLP64

Indicates the size in bits of basic C data types. Under LLP64 int and long data types are 32 bit, pointers and long long are 64 bits.

LP64

Indicates the size in bits of basic C data types. Under LP64 int types are 32 bits, all others are 64 bits.

LPAE

Large Physical Address Extension.

LSB

Least Significant Bit.

MESI

A cache coherency protocol with four states that are Modified, Exclusive, Shared and Invalid.

MMU

Memory Management Unit.

MOESI

A cache coherency protocol with five states that are Modified, Owned, Exclusive, Shared and Invalid.

Monitor mode

When EL3 is using AArch32, the PE mode in which the Secure Monitor must execute. This mode guards transitions between the Secure and Normal worlds.

MPU

Memory Protection Unit.

NEON

The ARM Advanced SIMD Extensions.

NIC

Network InterConnect.

Normal world

The execution environment when the processor is in the Non-secure state.

PCS

Procedure Call Standard.

PIPT

Physically Indexed, Physically Tagged.

PoC

Point of Coherency.

PoU

Point of Unification.

PSR

Program Status Register.

SCU

Snoop Control Unit.

Secure world

The execution environment when the processor is in the Secure State.

SIMD

Single Instruction, Multiple Data.

SMC

Secure Monitor Call. An ARM assembler instruction that causes an exception that is taken synchronously to EL3.

SMC32

32-bit SMC calling convention

SMC64

64-bit SMC calling convention

SMC Function Identifier

A 32-bit integer which identifies which function is being invoked by this SMC call. Passed in R0 or W0 to every SMC call

SMMU

System MMU.

SMP

Symmetric Multi-Processing.

SoC

System on Chip.

SP

Stack Pointer.

SPSR

Saved Program Status Register.

Streamline

A graphical performance analysis tool.

SVC

Supervisor Call instruction.

SYS

System Mode.

Thumb®

An instruction set extension to ARM.

Thumb-2

A technology extending the Thumb instruction set to support both 16-bit and 32-bit instructions.

TLB

Translation Lookaside Buffer.

TrustedOS

This is the operating system running in the Secure World. It supports the execution of trusted applications in Secure EL0. When EL3 is using AArch64 it executes in Secure EL1. When EL3 is using AArch32 it executes in Secure EL3 modes other than Monitor mode.

TrustZone®

The ARM security extension.

TTB

Translation Table Base.

TTBR

Translation Table Base Register.

UART

Universal Asynchronous Receiver/Transmitter.

UEFI

Unified Extensible Firmware Interface.

U-Boot

A Linux Bootloader.

UNK

Unknown.

UNKNOWN

Values in a register cannot be known before they are reset.

UNPREDICTABLE

The value taken cannot be predicted.

USR

User mode, a non-privileged processor mode.

VFP

The ARM floating-point instruction set. Before ARMv7, the VFP extension was called the Vector Floating-Point architecture, and was used for vector operations.

VIPT

Virtually Indexed, Physically Tagged.

VMID

Virtual Machine Identifier.

XN

Execute Never.

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