CoreSight ™ Technology SystemDesign Guide

Revision: r1p0

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CoreSight ™ Technology SystemDesign Guide

Revision: r1p0

Copyright © 2004, 2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this guide

Product revision status
Intended audience
Using this guide
Conventions
Further reading

Feedback on the product
Feedback on this guide

1. Introduction

1.1. About CoreSight systems

1.2. CoreSight features

1.2.1. Debug access
1.2.2. Cross Triggering
1.2.3. Trace

2. CoreSight Components and Systems

2.1. About CoreSight systems and components

2.2. CoreSight components

2.2.1. Buses
2.2.2. Control and access components
2.2.3. Trace sources
2.2.4. Trace Links
2.2.5. Trace sinks
2.2.6. External debug hardware and software

2.3. CoreSight system examples

2.3.1. Single core debug
2.3.2. Single source trace
2.3.3. Multi source trace in an single CPU system
2.3.4. Multi source trace in a multi-core system

2.4. Illegal structures

2.4.1. Stacked DAPs
2.4.2. Duplicated IDs
2.4.3. Feedback of source ID and data duplication

3. Features of CoreSight Technology and ETM Architectures

3.1. About CoreSight technology and ETMarchitectures features

3.2. CoreSight component data

3.2.1. DAP features
3.2.2. Source features
3.2.3. Link features
3.2.4. Sink features
3.2.5. Debug features

3.3. Architectural features of ARM tracesources

4. Debug Access

4.1. About debug access

4.2. Access to the system

4.2.1. JTAG direct to core access
4.2.2. DAP access

4.3. Mixed legacy and DAP debug

4.4. Debug activity across the chip

4.4.1. Direct links
4.4.2. Linking with an ECT

4.5. Typical trigger signals

4.5.1. CPU connections
4.5.2. ETM connections
4.5.3. Other trace source connections
4.5.4. TPIU and ETB connections

5. Trace Capture

5.1. About trace capture

5.1.1. Operation of a TCD

5.2. Designing your trace system

5.2.1. Differences between on-chip and off-chipstorage
5.2.2. Calculating the number of trace portpins
5.2.3. Calculating the size of ETB RAM required
5.2.4. ATB bandwidth

5.3. Using your system

5.3.1. Synchronization frequency
5.3.2. Using the ETB for profiling
5.3.3. Arbitration

6. Implementation

6.1. About implementation

6.2. Power Control

6.2.1. Multiple power domains
6.2.2. Intelligent Energy Management (IEM)

6.3. Power Domains and System Design

6.4. Power control enabled components

6.4.1. Debug Access Port (DAP)
6.4.2. Power for Trace Sources, ETM11CS, ETM9CS, and HTM

6.5. Debug and system power up

6.6. Clock domains

6.6.1. CoreSight system clock design
6.6.2. Clocking in an power control enabled system
6.6.3. CoreSight clocks and their inter-relationships

6.7. Resets

6.7.1. Connection of CSDK resets
6.7.2. Example CoreSight configurations

6.8. Tools controlled debug reset

6.9. Interface timing

6.9.1. Recommended ATB master interface timing parameters
6.9.2. Recommended ATB slave interface timing parameters

6.10. Timing, synthesis, and placement

6.10.1. DAP placement
6.10.2. ATB 1:1 bridge synthesis
6.10.3. TPIU TRACECLK generation

List of Figures

1. Key to timing diagram conventions
1.1. DAP connections inside a SoC
1.2. Cross triggering
1.3. Trace components
2.1. CoreSight system components
2.2. Structure of the CoreSight DAP component
2.3. HTM connected to a multi-layer AHBsystem
2.4. TPIU block diagram
2.5. ETB block diagram
2.6. Single CPU trace and Debug APB debugaccess
2.7. Single source trace with the TPIUformatting bypass
2.8. Full CoreSight trace with singlecore
2.9. Full system trace with ARM core andCoreSight compliant DSP
2.10. Unsupported DAP connection
2.11. Unsupported replicator and funnelconnection
2.12. Unsupported feedback loop
4.1. JTAG connection
4.2. JTAG core connected in parallel withDAP
4.3. Processor interaction
4.4. Signals of interest
5.1. Example system with ETB and TPIU
5.2. Use of the trigger to set a tracewindow
5.3. Effect of FIFO size on required tracebandwidth
5.4. System with two ETBs
5.5. Effect of frequency compared withinfrequent synchronization points
6.1. CoreSight system with no separatedebug domains
6.2. CoreSight system with a separatedebug power domain
6.3. ETM power and voltage domains
6.4. Unified power and voltage domains for ETM
6.5. HTM power and voltage domains
6.6. Unified power and voltage domainsfor HTM
6.7. Power up request and acknowledgementtiming
6.8. Clock domain interactions
6.9. Synchronous example clock configuration
6.10. Asynchronous example clock configuration
6.11. Reset handshaking mechanism
6.12. ATB master interface timing
6.13. ATB slave interface timing
6.14. Balancing TRACECLK
6.15. Timing balance

List of Tables

3.1. DAP component features for Debug Ports
3.2. DAP component features for Access Ports
3.3. Trace source component features
3.4. Trace source HTM and ITM features
3.5. Link component features, part 1
3.6. Link component features, part 2
3.7. Sink component features, part 1
3.8. Sink component features, part 2
3.9. Debug component features, part 1
3.10. Debug component features, part 2
3.11. ARM trace source component features, part 1
3.12. ARM trace source component features, part 2
4.1. CPU connections
4.2. ETM connections
4.3. HTM and ITM connections
4.4. TPIU and ETB connections
5.1. Effect of different tracing levels on ETM bandwidth requirements
6.1. Power up request and acknowledge signal connections
6.2. CSDK clocks
6.3. CSDK reset signals
6.4. ATB master interface parameters, input to register, registerto output
6.5. ATB slave interface parameters, input to register, registerto output

Proprietary Notice

Words and logos marked with ^® or ™ are registered trademarks or trademarksowned by ARM Limited, except as otherwise stated below in this proprietarynotice. Other brands and names mentioned herein may be the trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Where the term ARM is used it means “ARM or any of its subsidiariesas appropriate”.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision Non-Confidential	29September 2004	First release
Revision Non-Confidential	20July 2007	Updated for r1p0

Copyright © 2004, 2007 ARM Limited. All rights reserved.	ARM DGI 0012B
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