Glossary

This glossary describes some of the terms used in technical documents from ARM.

Abort

An exception caused by an illegal memory access. Aborts can be caused by the external memory system or by the memory-management hardware, that might include a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).

See Also Data abort, External abort and Prefetch abort.

Advanced eXtensible Interface (AXI)

A bus protocol that supports separate phases for address or control and data, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels, issuing multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure.

The AXI protocol includes optional extensions for signaling for low-power operation.

Advanced High-performance Bus (AHB)

A bus protocol with a fixed pipeline between the address or control and data phases. It supports a subset of the functionality of the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave implementations and ARM recommends using the AMBA AHB-Lite subset of the protocol.

See Also Advanced Microcontroller Bus Architecture and AHB-Lite.

Advanced Microcontroller Bus Architecture (AMBA)

The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides a strategy for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals. AMBA defines a common backbone for SoC modules, and therefore complements a reusable design methodology.

Advanced Peripheral Bus (APB)

A bus protocol that is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. It connects to the main system bus through a system-to-peripheral bus bridge that helps reduce system power consumption.

Advanced Trace Bus (ATB)

A bus used by trace devices to share CoreSight capture resources.

AHB

See Advanced High-performance Bus.

AHB Access Port (AHB-AP)

An optional component of the DAP that provides an AHB interface to a SoC.

AHB-AP

See AHB Access Port.

AHB-Lite

A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA AHB interface are implemented more efficiently using an AMBA AXI protocol interface.

Aligned

A data item stored at an address that is divisible by the number of bytes that defines its data size is said to be aligned. Aligned doublewords, words, and halfwords have addresses that are divisible by eight, four, and two respectively. The terms doubleword-aligned, word-aligned, and halfword-aligned therefore stipulate addresses that are divisible by eight, four, and two respectively. An aligned access is one where the address of the access is aligned to the size of an element of the access.

AMBA

See Advanced Microcontroller Bus Architecture.

APB

See Advanced Peripheral Bus.

APB Access Port (APB-AP)

An optional component of the DAP that provides an APB interface to a SoC, usually to its main functional buses.

APB-AP

See APB Access Port.

ATB

See Advanced Trace Bus.

ATB bridge

A synchronous ATB bridge provides a register slice that helps timing closure by adding a pipeline stage. It also provides a unidirectional link between two synchronous ATB domains.

An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks. It supports connection of components with ATB ports in different clock domains.

AXI

See Advanced eXtensible Interface.

Base register

A register specified by a load or store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the virtual address that is sent to memory.

Beat

Alternative word for an individual transfer within a burst. For example, an INCR4 burst comprises four beats.

See Also Burst.

Breakpoint

A breakpoint is a debug event triggered by the execution of a particular instruction. It is specified in terms of one or both of the address of the instruction and the state of the processor when the instruction is executed.

See Also Watchpoint.

Burst

A group of transfers to consecutive addresses. Because the addresses are consecutive, the device transmitting the data does not have to supply an address for any transfer after the first one. This increases the speed at which the burst occurs. If using an AMBA interface, the transmitting device controls the burst using signals that indicate the length of the burst and how the addresses are incremented.

See Also Beat.

Coprocessor

A processor that supplements the main processor to carry out additional functions that the main processor cannot perform. The ARM architecture defines an interface to up to 16 coprocessors, CP0-CP15 for use by ARM:

  • CP15 insturctions access the System Control processor

  • CP14 instructions access control registers for debug, trace, and execution environment features

  • CP10 an CP11 instruction space is for floating-point and Advanced SIMD instructions if supported.

CoreSight

ARM on-chip debug and trace components, that provide the infrastructure for monitoring, tracing, and debugging a complete system on chip.

See Also CoreSight ECT, CoreSight ETB, CoreSight ETM, Trace Funnel, and Trace Port Interface Unit (TPIU).

CoreSight ETB

CoreSight ETB is a trace sink that provides on-chip storage of trace data using a configurable sized RAM.

See Also CoreSight, CoreSight ETB, Embedded Trace Buffer, and Embedded Trace Macrocell.

Cross Trigger Interface (CTI)

Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.

Cross Trigger Matrix (CTM)

In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.

CTI

See Cross Trigger Interface.

CTM

See Cross Trigger Matrix.

DAP

See Debug Access Port.

DBGTAP

See Debug Test Access Port.

Debug Access Port (DAP)

A block that acts as a master on a system bus and provides access to the bus from an external debugger.

Debug Test Access Port (DBGTAP)

A debug control and data interface based on the IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.

Debugger

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

Device Validation Suite (DVS)

A set of tests to check the functionality of a device against the functionality defined in the Technical Reference Manual. For example these tests stress the Bus Interface Unit (BIU), low-level memory sub-system, pipeline, cache and Tightly Coupled Memory (TCM) behavior.

Digital Signal Processing (DSP)

A variety of algorithms to process signals that have been sampled and converted to digital form. Saturated arithmetic is often used in such algorithms.

DSM

See Design Simulation Model.

DSP

See Digital Signal Processing.

DVS

See Device Validation Suite.

ECT

See Embedded Cross Trigger.

Embedded Cross Trigger (ECT)

A modular system that supports the interaction and synchronization of multiple triggering events with an SoC.

Embedded Trace Buffer (ETB)

Provides on-chip storage of trace data using a configurable sized RAM.

Embedded Trace Macrocell (ETM)

A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.

EmbeddedICE logic

An on-chip logic block that provides TAP-based debug support for an ARM processor. It is accessed through the DAP on the ARM processor.

EmbeddedICE-RT

Hardware provided by an ARM processor to aid debugging in real-time.

Endianness

The scheme that determines the order of successive bytes of a data word when it is stored in memory.

ETB

See Embedded Trace Buffer.

ETM

See Embedded Trace Macrocell.

Event

In an ARM trace macrocell, event has a particular meaning and these events can be simple or complex:

Simple

An observable condition that a trace macrocell can use to control aspects of a trace.

Complex

A boolean combination of simple events that a trace macrocell can use to control aspects of a trace.

Exception

A mechanism to handle a fault or error event. For example, exceptions handle external interrupts and undefined instructions.

Formatter

In an ETB or TPIU, an internal input block that embeds the trace source ID in the data to create a single trace stream.

Half-rate clocking

In an ARM trace macrocell, dividing the trace clock by two so that the TPA can sample trace data signals on both the rising and falling edges of the trace clock. The primary purpose of half-rate clocking is to reduce the signal transition rate on the trace clock of an ASIC for very high-speed systems.

Host

A computer that provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

IEM

See Intelligent Energy Management.

Implementation-defined

Behavior that is not defined by the architecture, but is defined and documented by the implementation.

Implementation-specific

See Implementation-defined.

Imprecise tracing

In an ARM trace macrocell, a filtering configuration where instruction or data tracing can start or finish earlier or later than expected. Most imprecise cases cause tracing to start or finish later than expected.

For example, if TraceEnable is configured to use a counter so that tracing begins after the fourth write to a location in memory, the instruction that caused the fourth write is not traced, although subsequent instructions are. This is because the use of a counter in the TraceEnable configuration always results in imprecise tracing.

Instrumentation trace

A component for debugging real-time systems through a simple memory-mapped trace interface, providing printf style debugging.

Intelligent Energy Management (IEM)

An ARM technology that reduces device power consumption by dynamic voltage scaling and clock frequency variation.

Interrupt handler

See Exception handler.

Invalidate

Marking a cache line as being not valid, by clearing the valid bit to 0. This must be done whenever the line does not contain a valid cache entry. For example, after a cache flush all lines are invalid.

Jazelle state

In Jazelle state the processor executes Java bytecodes as part of a Java Virtual Machine (JVM).

See Also ARM state, Thumb state, and ThumbEE state.

JTAG Access Port (JTAG-AP)

An optional component of the DAP that provides debugger access to on-chip scan chains.

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells, such as a processor, an ETM, and a memory block integrated with application-specific logic.

MPU

See Memory Protection Unit.

Multi-ICE

A JTAG-based tool for debugging embedded systems.

Multi-master AHB

Typically a shared, not multi-layer, AHB interconnect scheme. More than one master connects to a single AMBA AHB link. In this case, the bus is implemented with a set of full AMBA AHB master interfaces. Masters that use the AMBA AHB-Lite protocol must connect through a wrapper to supply full AMBA AHB master signals to support multi-master operation.

Power-on reset

See Cold reset.

Prefetch abort

An indication from a memory system to the processor that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A Prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.

See Also Data abort, External abort and Abort.

Read

Memory operations that have the semantics of a load. See the ARM Architecture Reference Manual for more information.

RealView ICE

ARM JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.

Remapping

Changing the address of physical memory or devices after the application has started executing. This might be done to permit RAM to replace ROM when the initialization has completed.

Replicator

In an ARM trace macrocell, a replicator enables two trace sinks to be wired together and to operate independently on the same incoming trace stream. The input trace stream is output onto two independent ATB ports.

Reserved

Registers and instructions that are reserved are Unpredictable unless otherwise stated. Bit positions described as Reserved are UNK/SBZP.

SBO

See Should Be One.

SBOP

See Should Be One or Preserved.

SBZ

See Should Be Zero.

SBZP

See Should Be Zero or Preserved.

SDF

See Standard Delay Format.

Security hole

A mechanism that bypasses system protection.

Serial Wire Debug (SWD)

A debug implementation that uses a serial connection between the SoC and a debugger.

This connection normally requires a bi-directional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.

Serial Wire Debug Port (SWDP)

The interface for Serial Wire Debug.

Set

See Cache set.

Should Be One (SBO)

Software must write as 1, or all 1s for bit fields. Writing any other value produces Unpredictable results.

Should Be One or Preserved (SBOP)

Software must write as 1, or all 1s for bit fields, if the value is being written without having previously been read, or if the register has not been initialized. If the register has previously been read, software must preserve the field value by writing back the value that was read from the same field on the same processor.

If software writes a value that does not meet this requirement, the result is Unpredictable.

Hardware ignores writes to these fields.

Should Be Zero (SBZ)

Software must write as 0, or all 0s for bit fields. Writing any other value produces Unpredictable results.

Should Be Zero or Preserved (SBZP)

Software must write as 0, or all 0s for a bit field, if the value is being written without having previously been read, or if the register has not been initialized. If the register has previously been read, software must preserve the field value by writing back the value that was read from the same field on the same processor.

Subnormal value

In floating-point operation, a value in the range (-2Emin < x < 2Emin), except for plus or minus 0. In the IEEE 754 standard format for single-precision and double-precision operands, a subnormal value has a zero exponent and a nonzero fraction field. The IEEE 754 standard requires that the generation and manipulation of subnormal operands be performed with the same precision as normal operands.

Support code

In a floating-point implementation, system software that complements the hardware VFP implementation to provide compatibility with the IEEE 754 standard. The support code has a library of routines that perform supported functions, such as divide with unsupported inputs or inputs that might generate an exception, in addition to operations beyond the scope of the hardware. The support code has a set of exception handlers to process exceptional conditions in compliance with the IEEE 754 standard.

SVC

See Supervisor Call.

SWD

See Serial Wire Debug.

SWDP

See Serial Wire Debug Port.

SWI

See Supervisor Call.

Tag bits

In a cache implementation, bits [31:(L+S)] of a virtual address, where L = log2 (cache line length) and S = log2 (number of cache sets). A cache hit occurs if the tag bits of the virtual address supplied by the processor match the tag bits associated with a valid line in the selected cache set.

See Also Cache terminology diagram on the last page of this glossary.

TCD

See Trace Capture Device.

TPA

See Trace Port Analyzer.

TPIU

See Trace Port Interface Unit.

Trace Capture Device (TCD)

A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.

Trace funnel

In an ARM trace macrocell, a device that combines multiple trace sources onto a single bus.

See Also AHB Trace Macrocell, CoreSight, CoreSight ETM, and Embedded Trace Macrocell.

Trace hardware

A term for a device that contains an ARM trace macrocell.

Trace port

A port on a device, such as a processor or ASIC, used to output trace information.

Trace Port Analyzer (TPA)

A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.

Trace Port Interface Unit (TPIU)

Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.

Unaligned

An unaligned access is an access where the address of the access is not aligned to the size of an element of the access.

Undefined

Indicates an instruction that generates an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.

UNK

See Unknown.

UNK/SBOP

A field that is Unknown on reads and Should Be One or Preserved on writes.

UNK/SBZP

A field that is Unknown on reads and Should Be Zero or Preserved on writes.

Unknown

An Unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An Unknown value must not be a security hole.

UNP

See Unpredictable.

Unpredictable

For a processor means the behavior cannot be relied on. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.

Unpredictable

For an ARM trace macrocell, means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is Unpredictable. Unpredictable behavior can affect the behavior of the entire system, because the trace macrocell can cause the processor to enter debug state, and external outputs can be used for other purposes.

WA

See Write-Allocate cache.

Way

See Cache way.

WB

See Write-Back cache.

Word

A 32-bit data item. Words are normally word-aligned in ARM systems.

Write

Operations that have the semantics of a store. See the ARM Architecture Reference Manual for more information.

Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.ARM DGI 0012D
Non-ConfidentialID062610