6.7.1. Connection of CSDK resets

This section describes the CoreSight Technology resets:


You can connect all these signals to the same reset signal.

The system requires an external reset synchronizer that enables the resets to be asynchronously asserted, then synchronously deasserted.


Can be asserted at the same time as ATRESETn, and so it can come from the same reset signal.

If TRACECLKIN equals ATCLK, then you can use the output of the same synchronizer to deassert TRESETn.

If TRACECLKIN is not equal to ATCLK, then the system requires an additional reset synchronizer that asynchronously asserts the reset, but deasserts the reset synchronously to TRACECLKIN.


This is a true power-on reset signal for the SWJ-DP. It resets all the registers within the Debug Port clocked by TCK, but not part of the TAP state machine, reset by nTRST. It must only be driven LOW at power-on of the platform. To ensure that this signal is internally synchronized to TCK, you must fit an external reset synchronizer on nPOTRST.

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