6.9.1. Recommended ATB master interface timing parameters

Figure 6.12 shows the interface timing for the ATB master in a CoreSight system.

Figure 6.12. ATB master interface timing

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Table 6.4 lists the timing constraints that apply for the ATB master interface.

Table 6.4. ATB master interface parameters, input to register, register to output

Parameter Description Maximum Minimum
TisatcenmATCLKEN input setup to rising ATCLK -30%
TovatdatamRising ATCLK to ATDATAM valid 40% -
TovatinfmRising ATCLK to ATBYTESM and ATID and ID outputs valid 40% -
TovatconmRising ATCLK to ATB control outputs valid40% -
TisatconmATB control inputs setup to rising ATCLK-30%
TisatresetnATRESETn input setup to rising ATCLK-30%

Cycle percentages are with respect to the CoreSight component:

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