6.4.1. Debug Access Port (DAP)

The DAP supports implementation over the following different power domains with asynchronous interfaces between:

Each of these interfaces provides placeholders in the source code to enable the addition of signal clamps during implementation. You can enable the placeholders with Verilog `ifdef pragmas to use the clamping placeholders. The following Verilog `define must be present during compilation:

`define IEMSupport.

This `define instantiates a dummy Verilog module that describes the functionality of the clamp logic. This has the benefit that the component behaves appropriately for simulation and the implementation can include the correct library model with minimum overhead.

The same placeholders are used for signal clamps, for power-down, and level-shifters, if IEM support is implemented.

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