6.4.2. Power for Trace Sources, ETM11CS, ETM9CS, and HTM

A number of implementation options are possible for trace sources. The most power efficient solution for the organization of power domains, is also the most complex to implement for the trace sources. Therefore, this implementation is only likely in systems when a reduction in power consumption is critical.

The trace sources do not fit cleanly into a common power and voltage domain. Ideally, the CoreSight ETM and HTM exist within the debug power domain. This permits independent power-down of the trace components when there is no debug or trace in progress. However, both the ETM and HTM must be in the voltage domain of the component being traced. This is especially critical for the ETM because it must operate synchronously with its associated core and at the same speed. It is not possible to have an IEM enabled boundary between the CPU and ETM because there must be no asynchronous boundary. Figure 6.3 shows a configuration for the ETM, and Figure 6.5 shows a configuration for the HTM.

The following sections describes how to simplify the system design to address these complex implementation steps and remove the requirement for a separate voltage island:

ETM11CS, ETM9CS power

Figure 6.3 shows an ETM connected with separate power and voltage domains.

Figure 6.3. ETM power and voltage domains

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To simplify system design, it is recommended that you put the ETM in the core power domain, so that it is powered-down when the core is powered-down. Figure 6-4 shows how the power and voltage boundaries are then unified, and the clamp between the core and ETM is not required.

Figure 6.4. Unified power and voltage domains for ETM

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For more information on the implementation of clamps in the ETM11CS, see the CoreSight ETM 11 Technical Reference Manual and for the ETM9CS the CoreSight ETM 9 Technical Reference Manual.

HTM power

The HTM supports implementation over the following different power domains with asynchronous interfaces between:

  • The debug APB interface and the AHB clocked trace generation logic. There is an asynchronous interface between PCLKDBG and HCLK.

  • The AHB clocked trace generation logic and the ATB trace output. There is an asynchronous interface between HCLK and ATCLK.

PCLKDBG and ATCLK driven logic is synchronous, and both are common to the debug power domain. Signal clamps are implemented in the source code to enable the addition of signal clamps between the debug power domain and SoC power domain providing HCLK, during implementation.

To enable use of the clamping placeholders, the following Verilog `define must be present during compilation:

`define CSHTM_CLAMP_LOGIC.

This instantiates a dummy Verilog module that describes the functionality of the clamp logic. This has the benefit that the component behaves appropriately for simulation, and the implementation can include the correct library model with minimum overhead.

Figure 6.5 shows an HTM connected with separate power and voltage domains.

Figure 6.5. HTM power and voltage domains

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To simplify system design, it is recommended that you put the HTM in the SoC power domain, if SoC and Debug are independent, so it is powered-down when the SoC domain is powered-down. Figure 6.6 shows how the power and voltage boundaries are then unified.

Figure 6.6. Unified power and voltage domains for HTM

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