6.7.2. Example CoreSight configurations

Figure 6.9 shows a sample clock configuration for a typical CoreSight-enabled system.

In this configuration, ATCLK and the system interconnect AHB clock, HCLK, are equivalent.

ATCLK = HCLK = PSYSCLK.

PCLKDBG = DAPCLK. These are also synchronous to ATCLK:

You can make CTMCLK equal to ATCLK.

ATCLK, HCLK, PSYSCLK, PCLKDBG, DAPCLK, CoreCLK, CTI2:CTICLK, CTI3:CTICLK and CTMCLK are all synchronous.

Asynchronous clocks are:

Figure 6.9. Synchronous example clock configuration

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Figure 6.10 shows a sample clock configuration for a CoreSight-enabled system with multiple asynchronous clock domains.

In this configuration, ATCLK and the system interconnect AHB clock, HCLK, are asynchronous. In the following list one point is asynchronous to other points, with the exception of PCLKDBG and DAPCLK that must be synchronous to ATCLK:

Figure 6.10. Asynchronous example clock configuration

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