4.3.1. Debug memory overview

The DAP is setup with a ROM table located at address offsets 0x0000_0000 and 0x8000_0000 for system and APB-AP accesses respectively. Although the full address range is available for debug components, it is split into the following regions:

The upper half with PADDRDBG[31] equal to 1’b1 can only be reached by external debug tools accessing through the APB-AP. The ROM table is located at the bottom of this region as the BASE register within the APB-AP indicates.

The lower half, PADDRDBG[31] equal to 1’b0, can only be accessed from the system interface that is enforced through the restriction of the APB system input to the APB-MUX only accepting PADDRSYS[30:2]. This division of memory enables bypassing of lock-access mechanisms that can be used by debug components to prevent accidental damage to debug control registers. For more information on the use of PADDRDBG[31], see the CoreSight Architecture.

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