4.3.3. Debug memory decoding and the ROM table

It is advisable to place a ROM table for the debug system at the bottom of the debug address range for the CoreSight DK DAP, and one is already supplied at this fixed location. From this base address, offsets can be generated at 4KB intervals for allocation to CoreSight components present on the Debug APB. The address decoder for the bus must then correspondingly decode those offsets specified within the ROM table. Where features such as the bypassing of lock access, are implemented on PADDRDBG[31] being HIGH, the ROM table must be present at this offset location, that is 0x8000_0000 rather than 0x0000_0000 such as the APB-AP in the DAP.

To ensure that the address decoder for the Debug APB behaves in the same way for both types of accesses, the decoder must ignore PADDRDBG[31] but still decode all the remaining address bits, that is, PADDRDBG[30:12] even though the system accesses only have a limited range from 0x0000_0000.

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