6.2. Power control

CoreSight Technology enables improvements to energy efficiency through:

Implementation of these power control features is optional. During implementation, you can either turn off or improve the energy efficiency of debug logic in a system with CoreSight Technology. Your system might only support IEM in the ARM processor. You must decide during implementation whether it is necessary provide a separate power domain for the debug and trace logic in the SoC under development.

It is recommended that you implement CoreSight systems with a separate debug power and voltage domain:

You must also provide:

Power domain

Power domains refer to those areas of the SoC that can be completely powered- down independently of one another. A separate debug power domain is necessary to power-down the debug infrastructure, or power it up independently of the system or CPU. The SoC requires wire clamps between signals that join two independently-powered domains. These clamps hold signals at known static values between powered and unpowered domains. For production embedded systems, when the debugger does not require access to the system, the system can power-down the debug logic within the core and SoC to avoid unnecessary leakage associated with this logic.

Voltage domain

Voltage domains define the areas of an SoC running at a common voltage. You can implement Dynamic Voltage Scaling (DVS) throughout a voltage domain to permit the voltage to drop and still meet the stated performance requirement, therefore reducing power consumption. Communication between voltage domains requires level-shifting the voltage level signal clamping, Level Shift and Clamp (LSC). This guide assumes that only the CPU supports DVS, with debug and SoC domains supporting power-down only. In these scenarios, debug and SoC power domain interactions require clamps on the outputs from any block that can be powered-down, rather than LSCs.

It is normal that power and voltage domains are identical, because this significantly eases layout and placement of power grids within an SoC.

This section describes:

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