6.6. Clock domains

This section describes:

Table 6.2 lists the CoreSight Technology clocks

Table 6.2. CSDK clocks

Clock Description
ATCLKThis is the AMBA Trace Bus (ATB) clock.
CSRTCKReturn Test Clock, target pacing signal.
CSTCKThis is the clock signal generated by the DAP (JTAG-AP) to drive JTAG interfaces other components.
CTICLKThis is the cross trigger interface clock. It can be synchronous or asynchronous to CTMCLK.
DAPCLKThis is the Debug Access Port (DAP) internal clock. It must be equivalent to PCLKDBG.
CTMCLKThis is the cross trigger matrix clock. It can be synchronous or asynchronous to CTICLK.
HCLKThis is the system-facing AHB clock used by the DAP (AHB-AP). It is asynchronous to DAPCLK.
PCLKDBGThis is the Debug APB clock. It must be synchronous, that is, equivalent to slower than ATCLK.
PCLKSYSThis is the system slave facing APB clock used by the DAP (APB-Mux). It can be asynchronous to DAPCLK.
SWCLKTCKThis is the SWJ-DP clock driven from the external debugger. It is asynchronous to DAPCLK.
TRACECLKINThis is the Trace Port Interface Unit external trace clock input. It is asynchronous to ATCLK.


CoreClk is external to CoreSight clocks, driving one or more ARM microprocessors, and is used by the ETM to correctly synchronize to the processor activity.

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