6.7. Resets

This section describes:

Table 6.3 lists the CoreSight Technology reset signals.

Table 6.3. CSDK reset signals

ResetDescription
ATRESETnThis is the ATB reset. It resets all registers in the ATCLK domain. It is active LOW.
nCTIRESETThis is the CTI reset signal. It resets all registers clocked by CTICLK. It is active LOW.
DAPRESETnThis is the DAP internal reset. It must be equivalent to PCLKDBG. It is active LOW.
HRESETnThis is a SoC provided reset signal that resets all of the AMBA on-chip interconnect. You must use this signal to reset the DAP, AHB-AP, and AHB master port.
HTMHRESETnThis is the HTM reset signal. It is for resetting logic in the AHB domain of the HTM and must not be the same as HRESETn to enable the HTM to trace AHB resets.
nCSTRSTThis is an internally-generated reset signal, controlled and generated by the JTAG-AP to reset TAP controllers on connected components.
nSRSTOUTThis is an internally-generated reset signal, controlled and generated by the JTAG-AP intended to reset sub-systems associated with the TAP controllers on that scan-chain.
nCTMRESETThis is the CTM reset signal. It resets all registers clocked by CTMCLK. It is active LOW.
nPOTRSTThis is a true power-on reset signal to the DAP SWJ-DP. It must only reset at power-on. It is active LOW.
nTRSTThis is the SWJ-DP TAP state machine clock. It is asynchronous to DAPCLK.
PRESETDBGnThis is the Debug APB reset. It resets all registers clocked by PCLKDBG. It is active LOW.
PRESETSYSnThis is the DAP APB-Mux reset signal that resets the APB slave input. In a typical system where HCLK and PCLKSYS are equivalent, this is the same reset signal as HRESETn. It is active LOW.
TRESETnThis is the TPIU trace input reset signal. It is active LOW.

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