6.8. Tools controlled debug reset

The control and status register provides two bits for reset control of the debug domain, DAPRESETn, PRESETDBGn, ATRESETn. The SWJ-DP registers are in the always powered-on external interface side of the SWJ-DP, and therefore, the system can drive them to make reset requests to a system reset controller. Figure 6.9 shows the request and acknowledgement timing.

At time T1, a reset request is initiated. At time T2, the reset controller acknowledges that reset of the debug domain has completed. At time T3, the SWJ-DP deasserts the reset request to indicate that it is aware of the reset completion forcing the reset controller to deassert the reset acknowledgement at time T4:

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