6.10.3. TPIU TRACECLK generation

TRACECLK is a divided by two, exported version of TRACECLKIN. The reason for creating a half clock is that the limiting factor for both the Trace Out Port is the slew rate from a zero-to-one and one-to-zero. If it is possible to detect logic 1 and logic 0 on the exported clock within one cycle, then it is also possible to detect two different values on the exported data pins.

TRACECLK can be derived from the negative edge of TRACECLKIN to create a sample point within the centre of the stable data, TRACEDATA, TRACECTL, on each changing edge of TRACECLK irrespective of the operating frequency. This method does create a issues during clock-tree synthesis, layout and static timing analysis because of the placement of a negative-edge flop and the requirement for even mark to ratio clock source.

An alternative approach that reduces clock management issues is by fixing up the clock edges with respect to the clock by adding delays as appropriate to the signal paths after generation. The register that creates the divided by two clock is a standard positive-edge register that operates synchronously to the TRACEDATA and TRACECTL registers. This method simplifies synthesis in the early stages, and ensures when clock-tree synthesis is performed, all the registers are operating at the same time. To create the sample point at a stable point within the exported data, a you must add a delay to the path of TRACECLK between the register and the pad.

Figure 6.14 shows TRACECLK at different points within the design and its relationship to the data and control signals, TRACEDATA and TRACECTL. At the moment of creation from the final registers of the Trace Out port signals, all data edges are aligned as point A in Figure 6.14 shows.

All the signal paths to the pads are subject to delays as a result of the path lengths, at point B, from wire delay. These delays must be minimized where possible by placing the registers as close to the pads as possible. Each path must be re-balanced to remove the relative skew between signals by adding in equivalent delays. An extra delay must be incorporated on the TRACECLK path to ensure the waveform at point C is achieved and that the rising and falling edges of TRACECLK correspond to the centre of stable data on TRACECTL and TRACEDATA as Figure 6.15 shows.

Figure 6.14. Balancing TRACECLK

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Figure 6.15 shows how the rising and falling edges of TRACECLK correspond to the centre of stable data on TRACECTL and TRACEDATA at point C.

Figure 6.15. Timing balance

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